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-rw-r--r--testsuite/synth/slice01/slice04.vhdl27
-rw-r--r--testsuite/synth/slice01/slice05.vhdl33
-rw-r--r--testsuite/synth/slice01/slice06.vhdl28
-rw-r--r--testsuite/synth/slice01/slice07.vhdl20
-rwxr-xr-xtestsuite/synth/slice01/testsuite.sh4
5 files changed, 112 insertions, 0 deletions
diff --git a/testsuite/synth/slice01/slice04.vhdl b/testsuite/synth/slice01/slice04.vhdl
new file mode 100644
index 000000000..42127d7f9
--- /dev/null
+++ b/testsuite/synth/slice01/slice04.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity slice04 is
+ port (clk : std_logic;
+ dat : std_logic_vector (7 downto 0);
+ mask : std_logic_vector (1 downto 0);
+ res : out std_logic_vector (7 downto 0));
+end slice04;
+
+architecture behav of slice04 is
+ signal z : natural range 0 to 0;
+ signal mem : std_logic_vector (7 downto 0);
+begin
+ z <= to_integer(unsigned(mask));
+
+ process(clk)
+ variable hi, lo : natural;
+ begin
+ if rising_edge (clk) then
+ mem (z*3 + 7 downto z*3) <= dat;
+ end if;
+ end process;
+
+ res <= mem;
+end behav;
diff --git a/testsuite/synth/slice01/slice05.vhdl b/testsuite/synth/slice01/slice05.vhdl
new file mode 100644
index 000000000..ff5b2e1f5
--- /dev/null
+++ b/testsuite/synth/slice01/slice05.vhdl
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity slice05 is
+ port (clk : std_logic;
+ dat : std_logic_vector (7 downto 0);
+ mask : std_logic_vector (1 downto 0);
+ res : out std_logic_vector (7 downto 0));
+end;
+
+architecture behav of slice05 is
+ subtype nul_t is natural range 0 to 0;
+ signal z : nul_t;
+
+ procedure wr(d : inout std_logic_vector(7 downto 0);
+ v : std_logic_vector(7 downto 0);
+ p : nul_t) is
+ begin
+ d (p*3 + 7 downto p*3) := v;
+ end wr;
+begin
+ z <= to_integer(unsigned(mask));
+
+ process(clk)
+ variable mem : std_logic_vector (7 downto 0);
+ begin
+ if rising_edge (clk) then
+ wr (mem, dat, z + 0);
+ res <= mem;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/synth/slice01/slice06.vhdl b/testsuite/synth/slice01/slice06.vhdl
new file mode 100644
index 000000000..58f1e6f37
--- /dev/null
+++ b/testsuite/synth/slice01/slice06.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity slice06 is
+ port (clk : std_logic;
+ dat : std_logic_vector (7 downto 0);
+ mask : std_logic_vector (1 downto 0);
+ res : out std_logic_vector (7 downto 0));
+end;
+
+architecture behav of slice06 is
+ signal z : natural range 0 to 0;
+ signal mem : std_logic_vector (7 downto 0);
+begin
+ z <= to_integer(unsigned(mask));
+
+ process(clk)
+ variable hi, lo : natural;
+ begin
+ if rising_edge (clk) then
+ lo := z * 3;
+ mem (lo + 7 downto lo) <= dat;
+ end if;
+ end process;
+
+ res <= mem;
+end behav;
diff --git a/testsuite/synth/slice01/slice07.vhdl b/testsuite/synth/slice01/slice07.vhdl
new file mode 100644
index 000000000..abf321a46
--- /dev/null
+++ b/testsuite/synth/slice01/slice07.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity slice07 is
+ port (clk : std_ulogic);
+end;
+
+architecture rtl of slice07 is
+ signal sidx : natural range 0 to 0 := 0;
+begin
+ process(clk)
+ variable vmem : std_ulogic_vector(7 downto 0);
+ variable j : integer;
+ begin
+ if rising_edge(clk) then
+ j := sidx * 8;
+ vmem(j + 7 downto j) := x"ba";
+ end if;
+ end process;
+end;
diff --git a/testsuite/synth/slice01/testsuite.sh b/testsuite/synth/slice01/testsuite.sh
index 828ebcc62..c27d7e432 100755
--- a/testsuite/synth/slice01/testsuite.sh
+++ b/testsuite/synth/slice01/testsuite.sh
@@ -6,4 +6,8 @@ for t in slice01 slice02 slice03; do
synth_tb $t
done
+for t in slice04 slice05 slice06 slice07; do
+ synth_analyze $t
+done
+
echo "Test successful"