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author | Tristan Gingold <tgingold@free.fr> | 2019-07-23 07:34:52 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-07-23 07:34:52 +0200 |
commit | e0281345a5437282f287568b6fafa8519512b9dd (patch) | |
tree | 50c31d11b6c514602779d57fce0ec5e27e6788a0 /testsuite/synth/slice01/slice01.vhdl | |
parent | e073f75229d0abf04c8c40fc67391fbd8ea4a9a1 (diff) | |
download | ghdl-e0281345a5437282f287568b6fafa8519512b9dd.tar.gz ghdl-e0281345a5437282f287568b6fafa8519512b9dd.tar.bz2 ghdl-e0281345a5437282f287568b6fafa8519512b9dd.zip |
synth: add testcase for previous commit.
Diffstat (limited to 'testsuite/synth/slice01/slice01.vhdl')
-rw-r--r-- | testsuite/synth/slice01/slice01.vhdl | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/testsuite/synth/slice01/slice01.vhdl b/testsuite/synth/slice01/slice01.vhdl new file mode 100644 index 000000000..0aaeced74 --- /dev/null +++ b/testsuite/synth/slice01/slice01.vhdl @@ -0,0 +1,28 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity slice01 is + generic (w: natural := 4); + port (rst : std_logic; + clk : std_logic; + di : std_logic; + do : out std_logic_vector (w - 1 downto 0)); +end slice01; + +architecture behav of slice01 is + signal r : std_logic_vector (w - 1 downto 0); +begin + do <= r; + + process(clk) + begin + if rising_edge (clk) then + if rst = '1' then + r <= (others => '0'); + else + r (w - 2 downto 0) <= r (w - 1 downto 1); + r (w - 1) <= di; + end if; + end if; + end process; +end behav; |