synth: add testcase for previous commit.

3 files changed, 81 insertions, 0 deletions

diff --git a/testsuite/synth/slice01/slice01.vhdl b/testsuite/synth/slice01/slice01.vhdl
new file mode 100644
index 000000000..0aaeced74
--- /dev/null
+++ b/testsuite/synth/slice01/slice01.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity slice01 is
+  generic (w: natural := 4);
+  port (rst : std_logic;
+        clk : std_logic;
+        di : std_logic;
+        do : out std_logic_vector (w - 1 downto 0));
+end slice01;
+
+architecture behav of slice01 is
+  signal r : std_logic_vector (w - 1 downto 0);
+begin
+  do <= r;
+  
+  process(clk)
+  begin
+    if rising_edge (clk) then
+      if rst = '1' then
+        r <= (others => '0');
+      else
+        r (w - 2 downto 0) <= r (w - 1 downto 1);
+        r (w - 1) <= di;
+      end if;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/slice01/tb_slice01.vhdl b/testsuite/synth/slice01/tb_slice01.vhdl
new file mode 100644
index 000000000..3972c8899
--- /dev/null
+++ b/testsuite/synth/slice01/tb_slice01.vhdl
@@ -0,0 +1,37 @@
+entity tb_slice01 is
+end tb_slice01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_slice01 is
+  signal rst : std_logic;
+  signal clk : std_logic;
+  signal di : std_logic;
+  signal do : std_logic_vector (3 downto 0);
+begin
+  dut: entity work.slice01
+    generic map (w => 4)
+    port map (rst, clk, di, do);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+    constant b0 : std_logic_vector (3 downto 0) := "1101";
+  begin
+    rst <= '1';
+    pulse;
+    rst <= '0';
+    for i in b0'reverse_range loop
+      di <= b0 (i);
+      pulse;
+    end loop;
+    assert do = b0 severity error;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/slice01/testsuite.sh b/testsuite/synth/slice01/testsuite.sh
new file mode 100755
index 000000000..1729c688d
--- /dev/null
+++ b/testsuite/synth/slice01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in slice01; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+done
+
+echo "Test successful"