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author | Tristan Gingold <tgingold@free.fr> | 2020-02-18 18:44:42 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-02-18 18:45:07 +0100 |
commit | 393612fc52586d8eb8372f0ce3f05c162cfccfe2 (patch) | |
tree | 9a3f06bd59ba01c80b8012b1e3e52e7a4aa516d9 /testsuite/synth/ram01 | |
parent | 3689e0eb1d8b4a9689afa6f76187f1ecdc5ec458 (diff) | |
download | ghdl-393612fc52586d8eb8372f0ce3f05c162cfccfe2.tar.gz ghdl-393612fc52586d8eb8372f0ce3f05c162cfccfe2.tar.bz2 ghdl-393612fc52586d8eb8372f0ce3f05c162cfccfe2.zip |
testsuite/synth: merge ram01 to mem01, add NOTES.txt
Diffstat (limited to 'testsuite/synth/ram01')
-rw-r--r-- | testsuite/synth/ram01/sram01.vhdl | 29 | ||||
-rw-r--r-- | testsuite/synth/ram01/srom01.vhdl | 28 | ||||
-rw-r--r-- | testsuite/synth/ram01/tb_sram01.vhdl | 43 | ||||
-rw-r--r-- | testsuite/synth/ram01/tb_srom01.vhdl | 38 | ||||
-rwxr-xr-x | testsuite/synth/ram01/testsuite.sh | 16 |
5 files changed, 0 insertions, 154 deletions
diff --git a/testsuite/synth/ram01/sram01.vhdl b/testsuite/synth/ram01/sram01.vhdl deleted file mode 100644 index b4bfd0d2e..000000000 --- a/testsuite/synth/ram01/sram01.vhdl +++ /dev/null @@ -1,29 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity sram01 is - port ( - clk_i : std_logic; - addr_i : std_logic_vector(3 downto 0); - data_i : std_logic_vector(7 downto 0); - data_o : out std_logic_vector(7 downto 0); - wen_i : std_logic); -end sram01; - -architecture behav of sram01 is -begin - process (clk_i, addr_i) - type mem_type is array (0 to 15) of std_logic_vector (7 downto 0); - variable mem : mem_type; - variable addr : natural range mem_type'range; - begin - if rising_edge(clk_i) then - addr := to_integer (unsigned (addr_i)); - data_o <= mem (addr); - if wen_i = '1' then - mem (addr) := data_i; - end if; - end if; - end process; -end behav; diff --git a/testsuite/synth/ram01/srom01.vhdl b/testsuite/synth/ram01/srom01.vhdl deleted file mode 100644 index 1d8e70b64..000000000 --- a/testsuite/synth/ram01/srom01.vhdl +++ /dev/null @@ -1,28 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity srom01 is - port ( - clk_i : std_logic; - addr_i : std_logic_vector(3 downto 0); - data_o : out std_logic_vector(7 downto 0)); -end srom01; - -architecture behav of srom01 is -begin - process (clk_i, addr_i) - type mem_type is array (0 to 15) of std_logic_vector (7 downto 0); - constant mem : mem_type := ( - x"f0", x"e1", x"d2", x"c3", - x"b4", x"a5", x"96", x"87", - x"78", x"69", x"5a", x"4b", - x"3c", x"2d", x"1e", x"0f"); - variable addr : natural range mem_type'range; - begin - if rising_edge(clk_i) then - addr := to_integer (unsigned (addr_i)); - data_o <= mem (addr); - end if; - end process; -end behav; diff --git a/testsuite/synth/ram01/tb_sram01.vhdl b/testsuite/synth/ram01/tb_sram01.vhdl deleted file mode 100644 index 6fa0a7106..000000000 --- a/testsuite/synth/ram01/tb_sram01.vhdl +++ /dev/null @@ -1,43 +0,0 @@ -entity tb_sram01 is -end tb_sram01; - -library ieee; -use ieee.std_logic_1164.all; - -architecture behav of tb_sram01 is - signal addr : std_logic_vector(3 downto 0); - signal rdat : std_logic_vector(7 downto 0); - signal wdat : std_logic_vector(7 downto 0); - signal wen : std_logic; - signal clk : std_logic; -begin - dut: entity work.sram01 - port map (clk_i => clk, addr_i => addr, data_i => wdat, data_o => rdat, - wen_i => wen); - - process - procedure pulse is - begin - clk <= '0'; - wait for 1 ns; - clk <= '1'; - wait for 1 ns; - end pulse; - begin - addr <= "0000"; - wdat <= x"01"; - wen <= '1'; - pulse; - - addr <= "0001"; - wdat <= x"02"; - pulse; - - addr <= "0000"; - wen <= '0'; - pulse; - assert rdat = x"01" severity failure; - - wait; - end process; -end behav; diff --git a/testsuite/synth/ram01/tb_srom01.vhdl b/testsuite/synth/ram01/tb_srom01.vhdl deleted file mode 100644 index 530423a67..000000000 --- a/testsuite/synth/ram01/tb_srom01.vhdl +++ /dev/null @@ -1,38 +0,0 @@ -entity tb_srom01 is -end tb_srom01; - -library ieee; -use ieee.std_logic_1164.all; - -architecture behav of tb_srom01 is - signal addr : std_logic_vector(3 downto 0); - signal rdat : std_logic_vector(7 downto 0); - signal clk : std_logic; -begin - dut: entity work.srom01 - port map (clk_i => clk, addr_i => addr, data_o => rdat); - - process - procedure pulse is - begin - clk <= '0'; - wait for 1 ns; - clk <= '1'; - wait for 1 ns; - end pulse; - begin - addr <= "0000"; - pulse; - assert rdat = x"f0" severity failure; - - addr <= "0001"; - pulse; - assert rdat = x"e1" severity failure; - - addr <= "0100"; - pulse; - assert rdat = x"b4" severity failure; - - wait; - end process; -end behav; diff --git a/testsuite/synth/ram01/testsuite.sh b/testsuite/synth/ram01/testsuite.sh deleted file mode 100755 index 6254b1ab6..000000000 --- a/testsuite/synth/ram01/testsuite.sh +++ /dev/null @@ -1,16 +0,0 @@ -#! /bin/sh - -. ../../testenv.sh - -for t in sram01 srom01; do - analyze $t.vhdl tb_$t.vhdl - elab_simulate tb_$t - clean - - synth $t.vhdl -e $t > syn_$t.vhdl - analyze syn_$t.vhdl tb_$t.vhdl - elab_simulate tb_$t --ieee-asserts=disable-at-0 - clean -done - -echo "Test successful" |