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authorTristan Gingold <tgingold@free.fr>2020-02-18 18:44:42 +0100
committerTristan Gingold <tgingold@free.fr>2020-02-18 18:45:07 +0100
commit393612fc52586d8eb8372f0ce3f05c162cfccfe2 (patch)
tree9a3f06bd59ba01c80b8012b1e3e52e7a4aa516d9
parent3689e0eb1d8b4a9689afa6f76187f1ecdc5ec458 (diff)
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testsuite/synth: merge ram01 to mem01, add NOTES.txt
-rw-r--r--testsuite/synth/mem01/NOTES.txt9
-rw-r--r--testsuite/synth/mem01/sram01.vhdl (renamed from testsuite/synth/ram01/sram01.vhdl)0
-rw-r--r--testsuite/synth/mem01/srom01.vhdl (renamed from testsuite/synth/ram01/srom01.vhdl)0
-rw-r--r--testsuite/synth/mem01/tb_sram01.vhdl (renamed from testsuite/synth/ram01/tb_sram01.vhdl)0
-rw-r--r--testsuite/synth/mem01/tb_srom01.vhdl (renamed from testsuite/synth/ram01/tb_srom01.vhdl)0
-rwxr-xr-xtestsuite/synth/mem01/testsuite.sh2
-rw-r--r--testsuite/synth/mem02/NOTES.txt8
-rw-r--r--testsuite/synth/mem2d01/NOTES.txt7
-rwxr-xr-xtestsuite/synth/ram01/testsuite.sh16
9 files changed, 25 insertions, 17 deletions
diff --git a/testsuite/synth/mem01/NOTES.txt b/testsuite/synth/mem01/NOTES.txt
new file mode 100644
index 000000000..84edd5041
--- /dev/null
+++ b/testsuite/synth/mem01/NOTES.txt
@@ -0,0 +1,9 @@
+Tests for RAMs
+--------------
+
+rom1: asynchronous ROM
+srom01: Read (initialized ROM).
+sram01: Read+Write (at the same address).
+dpram1: Read+Write (using signals, without enables)
+dpram2: Read+Write (using a variable, without enables)
+dpram3: Read+Write (like dpram2 but downto)
diff --git a/testsuite/synth/ram01/sram01.vhdl b/testsuite/synth/mem01/sram01.vhdl
index b4bfd0d2e..b4bfd0d2e 100644
--- a/testsuite/synth/ram01/sram01.vhdl
+++ b/testsuite/synth/mem01/sram01.vhdl
diff --git a/testsuite/synth/ram01/srom01.vhdl b/testsuite/synth/mem01/srom01.vhdl
index 1d8e70b64..1d8e70b64 100644
--- a/testsuite/synth/ram01/srom01.vhdl
+++ b/testsuite/synth/mem01/srom01.vhdl
diff --git a/testsuite/synth/ram01/tb_sram01.vhdl b/testsuite/synth/mem01/tb_sram01.vhdl
index 6fa0a7106..6fa0a7106 100644
--- a/testsuite/synth/ram01/tb_sram01.vhdl
+++ b/testsuite/synth/mem01/tb_sram01.vhdl
diff --git a/testsuite/synth/ram01/tb_srom01.vhdl b/testsuite/synth/mem01/tb_srom01.vhdl
index 530423a67..530423a67 100644
--- a/testsuite/synth/ram01/tb_srom01.vhdl
+++ b/testsuite/synth/mem01/tb_srom01.vhdl
diff --git a/testsuite/synth/mem01/testsuite.sh b/testsuite/synth/mem01/testsuite.sh
index 8d0b840a5..073c69ea4 100755
--- a/testsuite/synth/mem01/testsuite.sh
+++ b/testsuite/synth/mem01/testsuite.sh
@@ -2,7 +2,7 @@
. ../../testenv.sh
-for t in rom1 dpram1 dpram2 dpram3; do
+for t in rom1 srom01 sram01 dpram1 dpram2 dpram3; do
analyze $t.vhdl tb_$t.vhdl
elab_simulate tb_$t
clean
diff --git a/testsuite/synth/mem02/NOTES.txt b/testsuite/synth/mem02/NOTES.txt
new file mode 100644
index 000000000..fa43cedc9
--- /dev/null
+++ b/testsuite/synth/mem02/NOTES.txt
@@ -0,0 +1,8 @@
+Tests for RAMs
+--------------
+
+dpram1: Read+Write (using a signal)
+ram3: not a RAM (whole content available on a port).
+ram4: not a RAM (reset).
+ram5: not a RAM (reset)
+ram6: not a RAM (whole content available).
diff --git a/testsuite/synth/mem2d01/NOTES.txt b/testsuite/synth/mem2d01/NOTES.txt
new file mode 100644
index 000000000..17ed281fb
--- /dev/null
+++ b/testsuite/synth/mem2d01/NOTES.txt
@@ -0,0 +1,7 @@
+Tests for RAMs
+--------------
+
+dpram1r: Read(2d)+Write(1d), using indexes
+dpram2r: Read(2d)+Write(1d), using slices.
+dpram2w: Read(1d)+Write(2d), using slices.
+memmux04: Read(2d)+Write(1d), enable on write, intermediate variable for read.
diff --git a/testsuite/synth/ram01/testsuite.sh b/testsuite/synth/ram01/testsuite.sh
deleted file mode 100755
index 6254b1ab6..000000000
--- a/testsuite/synth/ram01/testsuite.sh
+++ /dev/null
@@ -1,16 +0,0 @@
-#! /bin/sh
-
-. ../../testenv.sh
-
-for t in sram01 srom01; do
- analyze $t.vhdl tb_$t.vhdl
- elab_simulate tb_$t
- clean
-
- synth $t.vhdl -e $t > syn_$t.vhdl
- analyze syn_$t.vhdl tb_$t.vhdl
- elab_simulate tb_$t --ieee-asserts=disable-at-0
- clean
-done
-
-echo "Test successful"