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author | Tristan Gingold <tgingold@free.fr> | 2020-03-07 10:44:51 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-03-07 10:44:51 +0100 |
commit | ec0b123c0341074f815ea8087da2dbf4b4575e49 (patch) | |
tree | 0960ac0107eb234c137650d8ae863b340d13de7e /testsuite/synth/output01/output07.vhdl | |
parent | 87907d6da96eb4bab35e8eb7aabc481e9b32e04c (diff) | |
download | ghdl-ec0b123c0341074f815ea8087da2dbf4b4575e49.tar.gz ghdl-ec0b123c0341074f815ea8087da2dbf4b4575e49.tar.bz2 ghdl-ec0b123c0341074f815ea8087da2dbf4b4575e49.zip |
testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite/synth/output01/output07.vhdl')
-rw-r--r-- | testsuite/synth/output01/output07.vhdl | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/testsuite/synth/output01/output07.vhdl b/testsuite/synth/output01/output07.vhdl new file mode 100644 index 000000000..081f8f0f9 --- /dev/null +++ b/testsuite/synth/output01/output07.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity output07 is + port (clk : std_logic; + i : std_logic; + o : out std_logic_vector (1 downto 0) := "10"); +end output07; + +architecture behav of output07 is +begin + process (clk) + begin + if rising_edge(clk) then + o (0) <= i; + o (1) <= not i; + end if; + end process; +end behav; |