testsuite/synth: add a test for previous commit.

3 files changed, 59 insertions, 1 deletions

diff --git a/testsuite/synth/output01/output07.vhdl b/testsuite/synth/output01/output07.vhdl
new file mode 100644
index 000000000..081f8f0f9
--- /dev/null
+++ b/testsuite/synth/output01/output07.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity output07 is
+  port (clk : std_logic;
+        i : std_logic;
+        o : out std_logic_vector (1 downto 0) := "10");
+end output07;
+
+architecture behav of output07 is
+begin
+  process (clk)
+  begin
+    if rising_edge(clk) then
+      o (0) <= i;
+      o (1) <= not i;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/output01/tb_output07.vhdl b/testsuite/synth/output01/tb_output07.vhdl
new file mode 100644
index 000000000..af2f7f037
--- /dev/null
+++ b/testsuite/synth/output01/tb_output07.vhdl
@@ -0,0 +1,39 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tb_output07 is
+end tb_output07;
+
+architecture behav of tb_output07 is
+  signal i : std_logic;
+  signal clk : std_logic;
+  signal o : std_logic_vector (1 downto 0);
+begin
+  inst: entity work.output07
+    port map (clk => clk, i => i, o => o);
+
+  process
+    procedure pulse is
+    begin
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+      clk <= '0';
+    end pulse;
+  begin
+    clk <= '0';
+    wait for 1 ns;
+    assert o = "10" severity failure;
+
+    i <= '1';
+    pulse;
+    assert o = "01" severity failure;
+
+    i <= '0';
+    pulse;
+    assert o = "10" severity failure;
+
+    wait;
+  end process;
+end behav;
+
diff --git a/testsuite/synth/output01/testsuite.sh b/testsuite/synth/output01/testsuite.sh
index 063bb7111..a32d2c431 100755
--- a/testsuite/synth/output01/testsuite.sh
+++ b/testsuite/synth/output01/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in output01 output06; do
+for t in output01 output06 output07; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean