synth: add tests for partial assignment.

1 files changed, 23 insertions, 0 deletions

diff --git a/testsuite/synth/output01/output06.vhdl b/testsuite/synth/output01/output06.vhdl
new file mode 100644
index 000000000..0ececa86f
--- /dev/null
+++ b/testsuite/synth/output01/output06.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity output06 is
+  port (i : std_logic;
+        o : out std_logic_vector (3 downto 0));
+end output06;
+
+architecture behav of output06 is
+  signal s : std_logic_vector(3 downto 0);
+begin
+  process (i)
+  begin
+    s(0) <= i;
+    s (1) <= not i;
+    s (3) <= i;
+  end process;
+
+  s (2) <= '0';
+
+  o <= s;
+end behav;
+