From ae6d2b79e508684f189b6d8cc093dbb6f586f767 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Thu, 1 Aug 2019 05:10:56 +0200 Subject: synth: add tests for partial assignment. --- testsuite/synth/output01/output06.vhdl | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 testsuite/synth/output01/output06.vhdl (limited to 'testsuite/synth/output01/output06.vhdl') diff --git a/testsuite/synth/output01/output06.vhdl b/testsuite/synth/output01/output06.vhdl new file mode 100644 index 000000000..0ececa86f --- /dev/null +++ b/testsuite/synth/output01/output06.vhdl @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity output06 is + port (i : std_logic; + o : out std_logic_vector (3 downto 0)); +end output06; + +architecture behav of output06 is + signal s : std_logic_vector(3 downto 0); +begin + process (i) + begin + s(0) <= i; + s (1) <= not i; + s (3) <= i; + end process; + + s (2) <= '0'; + + o <= s; +end behav; + -- cgit v1.2.3