testsuite/synth: add a test for std_match

3 files changed, 44 insertions, 1 deletions

diff --git a/testsuite/synth/oper01/match01.vhdl b/testsuite/synth/oper01/match01.vhdl
new file mode 100644
index 000000000..7b4148fef
--- /dev/null
+++ b/testsuite/synth/oper01/match01.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity match01 is
+  port (v : std_ulogic_vector(11 downto 0);
+        r : out boolean);
+end match01;
+
+architecture behav of match01 is
+begin
+  r <= std_match(v, "1111----0000");
+end behav;
diff --git a/testsuite/synth/oper01/tb_match01.vhdl b/testsuite/synth/oper01/tb_match01.vhdl
new file mode 100644
index 000000000..e7c1a2b53
--- /dev/null
+++ b/testsuite/synth/oper01/tb_match01.vhdl
@@ -0,0 +1,30 @@
+entity tb_match01 is
+end tb_match01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_match01 is
+  signal l  : std_ulogic_vector(11 downto 0);
+  signal r  : boolean;
+begin
+  match01_1: entity work.match01
+    port map (l, r);
+
+  process
+  begin
+    l <= x"f00";
+    wait for 1 ns;
+    assert r severity failure;
+
+    l <= x"ff0";
+    wait for 1 ns;
+    assert r severity failure;
+
+    l <= x"ef0";
+    wait for 1 ns;
+    assert not r severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/oper01/testsuite.sh b/testsuite/synth/oper01/testsuite.sh
index 19c995cd1..6ffd137c4 100755
--- a/testsuite/synth/oper01/testsuite.sh
+++ b/testsuite/synth/oper01/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in cmp01; do
+for t in cmp01 match01; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t --ieee-asserts=disable-at-0
     clean