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-rw-r--r--testsuite/synth/oper01/tb_match01.vhdl30
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diff --git a/testsuite/synth/oper01/tb_match01.vhdl b/testsuite/synth/oper01/tb_match01.vhdl
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+++ b/testsuite/synth/oper01/tb_match01.vhdl
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+entity tb_match01 is
+end tb_match01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_match01 is
+ signal l : std_ulogic_vector(11 downto 0);
+ signal r : boolean;
+begin
+ match01_1: entity work.match01
+ port map (l, r);
+
+ process
+ begin
+ l <= x"f00";
+ wait for 1 ns;
+ assert r severity failure;
+
+ l <= x"ff0";
+ wait for 1 ns;
+ assert r severity failure;
+
+ l <= x"ef0";
+ wait for 1 ns;
+ assert not r severity failure;
+
+ wait;
+ end process;
+end behav;