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author | Tristan Gingold <tgingold@free.fr> | 2019-09-08 08:36:02 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-11 06:37:27 +0200 |
commit | 419d542accc0a0bd5f3daa833f202043ce6f480c (patch) | |
tree | 4a374481236e336367f72cdc5499081d8f46e785 /testsuite/synth/mem01/tb_dpram3.vhdl | |
parent | 1e1eab735ecad00ee663a68e3a5118e041c20739 (diff) | |
download | ghdl-419d542accc0a0bd5f3daa833f202043ce6f480c.tar.gz ghdl-419d542accc0a0bd5f3daa833f202043ce6f480c.tar.bz2 ghdl-419d542accc0a0bd5f3daa833f202043ce6f480c.zip |
testsuite/synth: rename arr02 to mem01
Diffstat (limited to 'testsuite/synth/mem01/tb_dpram3.vhdl')
-rw-r--r-- | testsuite/synth/mem01/tb_dpram3.vhdl | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/testsuite/synth/mem01/tb_dpram3.vhdl b/testsuite/synth/mem01/tb_dpram3.vhdl new file mode 100644 index 000000000..9cdbd8af7 --- /dev/null +++ b/testsuite/synth/mem01/tb_dpram3.vhdl @@ -0,0 +1,52 @@ +entity tb_dpram3 is +end tb_dpram3; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_dpram3 is + signal raddr : std_logic_vector(3 downto 0); + signal rdat : std_logic_vector(7 downto 0); + signal waddr : std_logic_vector(3 downto 0); + signal wdat : std_logic_vector(7 downto 0); + signal clk : std_logic; +begin + dut: entity work.dpram3 + port map (raddr => raddr, rdat => rdat, waddr => waddr, wdat => wdat, + clk => clk); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + raddr <= "0000"; + waddr <= x"a"; + wdat <= x"5a"; + pulse; + + raddr <= x"a"; + waddr <= x"7"; + wdat <= x"87"; + pulse; + assert rdat = x"5a" severity failure; + + raddr <= x"7"; + waddr <= x"1"; + wdat <= x"e1"; + pulse; + assert rdat = x"87" severity failure; + + raddr <= x"1"; + waddr <= x"3"; + wdat <= x"c3"; + pulse; + assert rdat = x"e1" severity failure; + + wait; + end process; +end behav; |