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author | Tristan Gingold <tgingold@free.fr> | 2019-10-15 06:43:26 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-10-15 06:43:26 +0200 |
commit | 001bdb593ff5d2413c3a3a39ee0b65fc20a27cd0 (patch) | |
tree | f0d003b3e17179f7531082f52d3a9e3d4d8b9ea4 /testsuite/synth/lib01/and2.vhdl | |
parent | acf68c6a935edaf9cd3f575a5606e8fc6bd0fecb (diff) | |
download | ghdl-001bdb593ff5d2413c3a3a39ee0b65fc20a27cd0.tar.gz ghdl-001bdb593ff5d2413c3a3a39ee0b65fc20a27cd0.tar.bz2 ghdl-001bdb593ff5d2413c3a3a39ee0b65fc20a27cd0.zip |
testsuite/synth: add a test for --work option within files.
Diffstat (limited to 'testsuite/synth/lib01/and2.vhdl')
-rw-r--r-- | testsuite/synth/lib01/and2.vhdl | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/testsuite/synth/lib01/and2.vhdl b/testsuite/synth/lib01/and2.vhdl new file mode 100644 index 000000000..e2d18ed02 --- /dev/null +++ b/testsuite/synth/lib01/and2.vhdl @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity and2 is + port (a, b : std_logic; + o : out std_logic); +end and2; + +architecture behav of and2 is +begin + o <= a and b; +end behav; |