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| author | Tristan Gingold <tgingold@free.fr> | 2020-04-30 07:50:02 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-04-30 07:50:02 +0200 |
| commit | e3eb603c236e68e8438c212656a73fb58a3632f8 (patch) | |
| tree | 7d043da7d459f590055a663ef614aca0782f6377 /testsuite/synth/issue962 | |
| parent | d4db650b2aa78fc2712505bdf92c89fe1bd345b4 (diff) | |
| download | ghdl-e3eb603c236e68e8438c212656a73fb58a3632f8.tar.gz ghdl-e3eb603c236e68e8438c212656a73fb58a3632f8.tar.bz2 ghdl-e3eb603c236e68e8438c212656a73fb58a3632f8.zip | |
testsuite/synth: add and adjust tests for signals default value. #1273
Diffstat (limited to 'testsuite/synth/issue962')
| -rw-r--r-- | testsuite/synth/issue962/ent2.vhdl | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/testsuite/synth/issue962/ent2.vhdl b/testsuite/synth/issue962/ent2.vhdl index 3c7993b1f..6f8b2c75d 100644 --- a/testsuite/synth/issue962/ent2.vhdl +++ b/testsuite/synth/issue962/ent2.vhdl @@ -3,6 +3,7 @@ end; architecture a of ent2 is signal x : integer; - signal y : integer := x / 2; + signal y : integer; begin + y <= x / 2; end; |