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| author | Tristan Gingold <tgingold@free.fr> | 2020-04-30 07:50:02 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-04-30 07:50:02 +0200 |
| commit | e3eb603c236e68e8438c212656a73fb58a3632f8 (patch) | |
| tree | 7d043da7d459f590055a663ef614aca0782f6377 | |
| parent | d4db650b2aa78fc2712505bdf92c89fe1bd345b4 (diff) | |
| download | ghdl-e3eb603c236e68e8438c212656a73fb58a3632f8.tar.gz ghdl-e3eb603c236e68e8438c212656a73fb58a3632f8.tar.bz2 ghdl-e3eb603c236e68e8438c212656a73fb58a3632f8.zip | |
testsuite/synth: add and adjust tests for signals default value. #1273
| -rw-r--r-- | testsuite/synth/issue1271/issue3.vhdl | 14 | ||||
| -rwxr-xr-x | testsuite/synth/issue1271/testsuite.sh | 1 | ||||
| -rw-r--r-- | testsuite/synth/issue953/ent.vhdl | 6 | ||||
| -rw-r--r-- | testsuite/synth/issue962/ent2.vhdl | 3 |
4 files changed, 21 insertions, 3 deletions
diff --git a/testsuite/synth/issue1271/issue3.vhdl b/testsuite/synth/issue1271/issue3.vhdl new file mode 100644 index 000000000..3724dc464 --- /dev/null +++ b/testsuite/synth/issue1271/issue3.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity issue is + port + (i_foo : in std_logic; + o_foo : out std_logic); +end entity issue; + +architecture beh of issue is + signal k_foo : std_logic := i_foo; +begin + o_foo <= k_foo xor '0'; +end architecture; diff --git a/testsuite/synth/issue1271/testsuite.sh b/testsuite/synth/issue1271/testsuite.sh index b352bb675..44c78d7bd 100755 --- a/testsuite/synth/issue1271/testsuite.sh +++ b/testsuite/synth/issue1271/testsuite.sh @@ -4,5 +4,6 @@ synth_failure issue.vhdl -e synth_failure issue2.vhdl -e +synth_failure issue3.vhdl -e echo "Test successful" diff --git a/testsuite/synth/issue953/ent.vhdl b/testsuite/synth/issue953/ent.vhdl index 72c7988b2..d7457f4b8 100644 --- a/testsuite/synth/issue953/ent.vhdl +++ b/testsuite/synth/issue953/ent.vhdl @@ -7,7 +7,9 @@ end; architecture a of ent is signal x : unsigned(7 downto 0); - signal y : unsigned(7 downto 0) := x / 2; - signal z : unsigned(15 downto 0) := x * 2; + signal y : unsigned(7 downto 0); + signal z : unsigned(15 downto 0); begin + y <= x / 2; + z <= x * 2; end; diff --git a/testsuite/synth/issue962/ent2.vhdl b/testsuite/synth/issue962/ent2.vhdl index 3c7993b1f..6f8b2c75d 100644 --- a/testsuite/synth/issue962/ent2.vhdl +++ b/testsuite/synth/issue962/ent2.vhdl @@ -3,6 +3,7 @@ end; architecture a of ent2 is signal x : integer; - signal y : integer := x / 2; + signal y : integer; begin + y <= x / 2; end; |