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author | Tristan Gingold <tgingold@free.fr> | 2023-03-14 08:18:13 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2023-03-14 08:18:13 +0100 |
commit | ea460cb31034202c6d6d3fd720126fd0bedd8820 (patch) | |
tree | b476a8a2700fa51ff7caadab89d7d3c27ed0d9d8 /testsuite/synth/issue2390/top.vhdl | |
parent | e4740a99eb4db83bfbc212a699745d2d51494554 (diff) | |
download | ghdl-ea460cb31034202c6d6d3fd720126fd0bedd8820.tar.gz ghdl-ea460cb31034202c6d6d3fd720126fd0bedd8820.tar.bz2 ghdl-ea460cb31034202c6d6d3fd720126fd0bedd8820.zip |
testsuite/synth: add a test for #2390
Diffstat (limited to 'testsuite/synth/issue2390/top.vhdl')
-rw-r--r-- | testsuite/synth/issue2390/top.vhdl | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/testsuite/synth/issue2390/top.vhdl b/testsuite/synth/issue2390/top.vhdl new file mode 100644 index 000000000..5c08f590c --- /dev/null +++ b/testsuite/synth/issue2390/top.vhdl @@ -0,0 +1,29 @@ +library ieee; +context ieee.ieee_std_context; +use work.uCPUtypes.all; + +entity top is + port ( + rst, clk : in logic; + display : out unsigned_byte; + stb : out logic + ); +end entity top; + +architecture mixed of top is + signal rom_addr, ram_addr, ram_data : unsigned_byte; + signal rom_data : code_word; + signal wr_en : logic; +begin + +stb <= '1' when wr_en = '1' and ram_addr = x"00" else '0'; + +display <= ram_data; + +CPU_instance: entity work.uCPU(RTL) port map (rst, clk, rom_addr, rom_data, ram_addr, ram_data, wr_en); + +ROM_instance: entity work.ROM(RTL) port map (rom_addr, rom_data, '1'); + +RAM_instance: entity work.RAM(RTL) port map (clk, ram_addr, ram_data, wr_en); + +end architecture mixed; |