From ea460cb31034202c6d6d3fd720126fd0bedd8820 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 14 Mar 2023 08:18:13 +0100
Subject: testsuite/synth: add a test for #2390

---
 testsuite/synth/issue2390/top.vhdl | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 testsuite/synth/issue2390/top.vhdl

(limited to 'testsuite/synth/issue2390/top.vhdl')

diff --git a/testsuite/synth/issue2390/top.vhdl b/testsuite/synth/issue2390/top.vhdl
new file mode 100644
index 000000000..5c08f590c
--- /dev/null
+++ b/testsuite/synth/issue2390/top.vhdl
@@ -0,0 +1,29 @@
+library ieee;
+context ieee.ieee_std_context;
+use work.uCPUtypes.all;
+
+entity top is
+  port (
+    rst, clk : in logic;
+    display : out unsigned_byte;
+    stb : out logic
+  );
+end entity top;
+
+architecture mixed of top is
+  signal rom_addr, ram_addr, ram_data : unsigned_byte;
+  signal rom_data : code_word;
+  signal wr_en : logic;
+begin
+
+stb <= '1' when wr_en = '1' and ram_addr = x"00" else '0';
+
+display <= ram_data;
+
+CPU_instance: entity work.uCPU(RTL) port map (rst, clk, rom_addr, rom_data, ram_addr, ram_data, wr_en);
+
+ROM_instance: entity work.ROM(RTL) port map (rom_addr, rom_data, '1');
+
+RAM_instance: entity work.RAM(RTL) port map (clk, ram_addr, ram_data, wr_en);
+
+end architecture mixed;
-- 
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