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author | Tristan Gingold <tgingold@free.fr> | 2022-11-02 18:28:33 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-11-02 20:58:22 +0100 |
commit | 0d61fecf1249a5c2ae83d933274ee9a638f6ec69 (patch) | |
tree | bb38b5a7c0434c736e2b9dcf66e06914646aa6b0 /testsuite/synth/issue2237/implicit_wide2.vhdl | |
parent | cea058eb61d7b90ac8e2fcc41f2a42be8f330e68 (diff) | |
download | ghdl-0d61fecf1249a5c2ae83d933274ee9a638f6ec69.tar.gz ghdl-0d61fecf1249a5c2ae83d933274ee9a638f6ec69.tar.bz2 ghdl-0d61fecf1249a5c2ae83d933274ee9a638f6ec69.zip |
testsuite/synth: add tests for #2237
Diffstat (limited to 'testsuite/synth/issue2237/implicit_wide2.vhdl')
-rw-r--r-- | testsuite/synth/issue2237/implicit_wide2.vhdl | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/testsuite/synth/issue2237/implicit_wide2.vhdl b/testsuite/synth/issue2237/implicit_wide2.vhdl new file mode 100644 index 000000000..efcff0ce2 --- /dev/null +++ b/testsuite/synth/issue2237/implicit_wide2.vhdl @@ -0,0 +1,48 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity implicit_wide2 is +port ( + clk : in std_logic; + gate : in std_logic; + + d1 : in std_logic_vector(1 downto 0); + q1 : out std_logic_vector(1 downto 0); + q2 : out std_logic_vector(1 downto 0); + q3 : out std_logic_vector(1 downto 0); + + d2 : in unsigned(1 downto 0); + q4 : out unsigned(1 downto 0); + q5 : out unsigned(1 downto 0); + q6 : out unsigned(1 downto 0); + + d3 : in signed(1 downto 0); + q7 : out signed(1 downto 0); + q8 : out signed(1 downto 0); + q9 : out signed(1 downto 0) +); +end entity; + +architecture behav of implicit_wide2 is +begin + + process(clk) + begin + if rising_edge(clk) then + q1 <= gate and d1; + q2 <= gate or d1; + q3 <= gate xor d1; + + q4 <= gate and d2; + q5 <= gate or d2; + q6 <= gate xor d2; + + q7 <= gate and d3; + q8 <= gate or d3; + q9 <= gate xor d3; + end if; + end process; + +end architecture; + |