testsuite/synth: add tests for #2237

9 files changed, 746 insertions, 0 deletions

diff --git a/testsuite/synth/issue2237/implicit_wide.vhdl b/testsuite/synth/issue2237/implicit_wide.vhdl
new file mode 100644
index 000000000..7f3f1388a
--- /dev/null
+++ b/testsuite/synth/issue2237/implicit_wide.vhdl
@@ -0,0 +1,48 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity implicit_wide is
+port (
+	clk : in std_logic;
+	gate : in std_logic;
+
+	d1 : in std_logic_vector(1 downto 0);
+	q1 : out std_logic_vector(1 downto 0);
+	q2 : out std_logic_vector(1 downto 0);
+	q3 : out std_logic_vector(1 downto 0);
+
+	d2 : in unsigned(1 downto 0);
+	q4 : out unsigned(1 downto 0);
+	q5 : out unsigned(1 downto 0);
+	q6 : out unsigned(1 downto 0);
+
+	d3 : in signed(1 downto 0);
+	q7 : out signed(1 downto 0);
+	q8 : out signed(1 downto 0);
+	q9 : out signed(1 downto 0)
+);
+end entity;
+
+architecture behav of implicit_wide is
+begin
+
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			q1 <= d1 and gate;
+			q2 <= d1 or gate;
+			q3 <= d1 xor gate;
+
+			q4 <= d2 and gate;
+			q5 <= d2 or gate;
+			q6 <= d2 xor gate;
+
+			q7 <= d3 and gate;
+			q8 <= d3 or gate;
+			q9 <= d3 xor gate;
+		end if;
+	end process;
+
+end architecture;
+
diff --git a/testsuite/synth/issue2237/implicit_wide2.vhdl b/testsuite/synth/issue2237/implicit_wide2.vhdl
new file mode 100644
index 000000000..efcff0ce2
--- /dev/null
+++ b/testsuite/synth/issue2237/implicit_wide2.vhdl
@@ -0,0 +1,48 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity implicit_wide2 is
+port (
+	clk : in std_logic;
+	gate : in std_logic;
+
+	d1 : in std_logic_vector(1 downto 0);
+	q1 : out std_logic_vector(1 downto 0);
+	q2 : out std_logic_vector(1 downto 0);
+	q3 : out std_logic_vector(1 downto 0);
+
+	d2 : in unsigned(1 downto 0);
+	q4 : out unsigned(1 downto 0);
+	q5 : out unsigned(1 downto 0);
+	q6 : out unsigned(1 downto 0);
+
+	d3 : in signed(1 downto 0);
+	q7 : out signed(1 downto 0);
+	q8 : out signed(1 downto 0);
+	q9 : out signed(1 downto 0)
+);
+end entity;
+
+architecture behav of implicit_wide2 is
+begin
+
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			q1 <= gate and d1;
+			q2 <= gate or d1;
+			q3 <= gate xor d1;
+
+			q4 <= gate and d2;
+			q5 <= gate or d2;
+			q6 <= gate xor d2;
+
+			q7 <= gate and d3;
+			q8 <= gate or d3;
+			q9 <= gate xor d3;
+		end if;
+	end process;
+
+end architecture;
+
diff --git a/testsuite/synth/issue2237/implicit_wide3.vhdl b/testsuite/synth/issue2237/implicit_wide3.vhdl
new file mode 100644
index 000000000..c1e55505d
--- /dev/null
+++ b/testsuite/synth/issue2237/implicit_wide3.vhdl
@@ -0,0 +1,48 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity implicit_wide3 is
+port (
+	clk : in std_logic;
+	gate : in std_logic;
+
+	d1 : in std_logic_vector(1 downto 0);
+	q1 : out std_logic_vector(1 downto 0);
+	q2 : out std_logic_vector(1 downto 0);
+	q3 : out std_logic_vector(1 downto 0);
+
+	d2 : in unsigned(1 downto 0);
+	q4 : out unsigned(1 downto 0);
+	q5 : out unsigned(1 downto 0);
+	q6 : out unsigned(1 downto 0);
+
+	d3 : in signed(1 downto 0);
+	q7 : out signed(1 downto 0);
+	q8 : out signed(1 downto 0);
+	q9 : out signed(1 downto 0)
+);
+end entity;
+
+architecture behav of implicit_wide3 is
+begin
+
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			q1 <= d1 nand gate;
+			q2 <= d1 nor gate;
+			q3 <= d1 xnor gate;
+
+			q4 <= d2 nand gate;
+			q5 <= d2 nor gate;
+			q6 <= d2 xnor gate;
+
+			q7 <= d3 nand gate;
+			q8 <= d3 nor gate;
+			q9 <= d3 xnor gate;
+		end if;
+	end process;
+
+end architecture;
+
diff --git a/testsuite/synth/issue2237/implicit_wide4.vhdl b/testsuite/synth/issue2237/implicit_wide4.vhdl
new file mode 100644
index 000000000..8e3b9e126
--- /dev/null
+++ b/testsuite/synth/issue2237/implicit_wide4.vhdl
@@ -0,0 +1,48 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity implicit_wide4 is
+port (
+	clk : in std_logic;
+	gate : in std_logic;
+
+	d1 : in std_logic_vector(1 downto 0);
+	q1 : out std_logic_vector(1 downto 0);
+	q2 : out std_logic_vector(1 downto 0);
+	q3 : out std_logic_vector(1 downto 0);
+
+	d2 : in unsigned(1 downto 0);
+	q4 : out unsigned(1 downto 0);
+	q5 : out unsigned(1 downto 0);
+	q6 : out unsigned(1 downto 0);
+
+	d3 : in signed(1 downto 0);
+	q7 : out signed(1 downto 0);
+	q8 : out signed(1 downto 0);
+	q9 : out signed(1 downto 0)
+);
+end entity;
+
+architecture behav of implicit_wide4 is
+begin
+
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			q1 <= gate nand d1;
+			q2 <= gate nor d1;
+			q3 <= gate xnor d1;
+
+			q4 <= gate nand d2;
+			q5 <= gate nor d2;
+			q6 <= gate xnor d2;
+
+			q7 <= gate nand d3;
+			q8 <= gate nor d3;
+			q9 <= gate xnor d3;
+		end if;
+	end process;
+
+end architecture;
+
diff --git a/testsuite/synth/issue2237/tb_implicit_wide.vhdl b/testsuite/synth/issue2237/tb_implicit_wide.vhdl
new file mode 100644
index 000000000..1b7a1fd9e
--- /dev/null
+++ b/testsuite/synth/issue2237/tb_implicit_wide.vhdl
@@ -0,0 +1,136 @@
+entity tb_implicit_wide is
+end tb_implicit_wide;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of tb_implicit_wide is
+  signal clk  : std_logic;
+  signal gate : std_logic;
+  signal d1   : std_logic_vector(1 downto 0);
+  signal q1   : std_logic_vector(1 downto 0);
+  signal q2   : std_logic_vector(1 downto 0);
+  signal q3   : std_logic_vector(1 downto 0);
+  signal d2   : unsigned(1 downto 0);
+  signal q4   : unsigned(1 downto 0);
+  signal q5   : unsigned(1 downto 0);
+  signal q6   : unsigned(1 downto 0);
+  signal d3   : signed(1 downto 0);
+  signal q7   : signed(1 downto 0);
+  signal q8   : signed(1 downto 0);
+  signal q9   : signed(1 downto 0);
+begin
+  dut: entity work.implicit_wide
+    port map (
+      clk  => clk,
+      gate => gate,
+      d1   => d1,
+      q1   => q1,
+      q2   => q2,
+      q3   => q3,
+      d2   => d2,
+      q4   => q4,
+      q5   => q5,
+      q6   => q6,
+      d3   => d3,
+      q7   => q7,
+      q8   => q8,
+      q9   => q9);
+  
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    d1 <= "00";
+    d2 <= "00";
+    d3 <= "00";
+
+    gate <= '0';
+    pulse;
+    assert q1 = "00" severity failure;
+    assert q2 = "00" severity failure;
+    assert q3 = "00" severity failure;
+    assert q4 = "00" severity failure;
+    assert q5 = "00" severity failure;
+    assert q6 = "00" severity failure;
+    assert q7 = "00" severity failure;
+    assert q8 = "00" severity failure;
+    assert q9 = "00" severity failure;
+
+    gate <= '1';
+    pulse;
+    assert q1 = "00" severity failure;
+    assert q2 = "11" severity failure;
+    assert q3 = "11" severity failure;
+    assert q4 = "00" severity failure;
+    assert q5 = "11" severity failure;
+    assert q6 = "11" severity failure;
+    assert q7 = "00" severity failure;
+    assert q8 = "11" severity failure;
+    assert q9 = "11" severity failure;
+
+    d1 <= "01";
+    d2 <= "01";
+    d3 <= "01";
+
+    gate <= '0';
+    pulse;
+    assert q1 = "00" severity failure;
+    assert q2 = "01" severity failure;
+    assert q3 = "01" severity failure;
+    assert q4 = "00" severity failure;
+    assert q5 = "01" severity failure;
+    assert q6 = "01" severity failure;
+    assert q7 = "00" severity failure;
+    assert q8 = "01" severity failure;
+    assert q9 = "01" severity failure;
+
+    gate <= '1';
+    pulse;
+    assert q1 = "01" severity failure;
+    assert q2 = "11" severity failure;
+    assert q3 = "10" severity failure;
+    assert q4 = "01" severity failure;
+    assert q5 = "11" severity failure;
+    assert q6 = "10" severity failure;
+    assert q7 = "01" severity failure;
+    assert q8 = "11" severity failure;
+    assert q9 = "10" severity failure;
+
+    d1 <= "10";
+    d2 <= "10";
+    d3 <= "10";
+
+    gate <= '0';
+    pulse;
+    assert q1 = "00" severity failure;
+    assert q2 = "10" severity failure;
+    assert q3 = "10" severity failure;
+    assert q4 = "00" severity failure;
+    assert q5 = "10" severity failure;
+    assert q6 = "10" severity failure;
+    assert q7 = "00" severity failure;
+    assert q8 = "10" severity failure;
+    assert q9 = "10" severity failure;
+
+    gate <= '1';
+    pulse;
+    assert q1 = "10" severity failure;
+    assert q2 = "11" severity failure;
+    assert q3 = "01" severity failure;
+    assert q4 = "10" severity failure;
+    assert q5 = "11" severity failure;
+    assert q6 = "01" severity failure;
+    assert q7 = "10" severity failure;
+    assert q8 = "11" severity failure;
+    assert q9 = "01" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue2237/tb_implicit_wide2.vhdl b/testsuite/synth/issue2237/tb_implicit_wide2.vhdl
new file mode 100644
index 000000000..e4ff87e81
--- /dev/null
+++ b/testsuite/synth/issue2237/tb_implicit_wide2.vhdl
@@ -0,0 +1,136 @@
+entity tb_implicit_wide2 is
+end tb_implicit_wide2;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of tb_implicit_wide2 is
+  signal clk  : std_logic;
+  signal gate : std_logic;
+  signal d1   : std_logic_vector(1 downto 0);
+  signal q1   : std_logic_vector(1 downto 0);
+  signal q2   : std_logic_vector(1 downto 0);
+  signal q3   : std_logic_vector(1 downto 0);
+  signal d2   : unsigned(1 downto 0);
+  signal q4   : unsigned(1 downto 0);
+  signal q5   : unsigned(1 downto 0);
+  signal q6   : unsigned(1 downto 0);
+  signal d3   : signed(1 downto 0);
+  signal q7   : signed(1 downto 0);
+  signal q8   : signed(1 downto 0);
+  signal q9   : signed(1 downto 0);
+begin
+  dut: entity work.implicit_wide2
+    port map (
+      clk  => clk,
+      gate => gate,
+      d1   => d1,
+      q1   => q1,
+      q2   => q2,
+      q3   => q3,
+      d2   => d2,
+      q4   => q4,
+      q5   => q5,
+      q6   => q6,
+      d3   => d3,
+      q7   => q7,
+      q8   => q8,
+      q9   => q9);
+  
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    d1 <= "00";
+    d2 <= "00";
+    d3 <= "00";
+
+    gate <= '0';
+    pulse;
+    assert q1 = "00" severity failure;
+    assert q2 = "00" severity failure;
+    assert q3 = "00" severity failure;
+    assert q4 = "00" severity failure;
+    assert q5 = "00" severity failure;
+    assert q6 = "00" severity failure;
+    assert q7 = "00" severity failure;
+    assert q8 = "00" severity failure;
+    assert q9 = "00" severity failure;
+
+    gate <= '1';
+    pulse;
+    assert q1 = "00" severity failure;
+    assert q2 = "11" severity failure;
+    assert q3 = "11" severity failure;
+    assert q4 = "00" severity failure;
+    assert q5 = "11" severity failure;
+    assert q6 = "11" severity failure;
+    assert q7 = "00" severity failure;
+    assert q8 = "11" severity failure;
+    assert q9 = "11" severity failure;
+
+    d1 <= "01";
+    d2 <= "01";
+    d3 <= "01";
+
+    gate <= '0';
+    pulse;
+    assert q1 = "00" severity failure;
+    assert q2 = "01" severity failure;
+    assert q3 = "01" severity failure;
+    assert q4 = "00" severity failure;
+    assert q5 = "01" severity failure;
+    assert q6 = "01" severity failure;
+    assert q7 = "00" severity failure;
+    assert q8 = "01" severity failure;
+    assert q9 = "01" severity failure;
+
+    gate <= '1';
+    pulse;
+    assert q1 = "01" severity failure;
+    assert q2 = "11" severity failure;
+    assert q3 = "10" severity failure;
+    assert q4 = "01" severity failure;
+    assert q5 = "11" severity failure;
+    assert q6 = "10" severity failure;
+    assert q7 = "01" severity failure;
+    assert q8 = "11" severity failure;
+    assert q9 = "10" severity failure;
+
+    d1 <= "10";
+    d2 <= "10";
+    d3 <= "10";
+
+    gate <= '0';
+    pulse;
+    assert q1 = "00" severity failure;
+    assert q2 = "10" severity failure;
+    assert q3 = "10" severity failure;
+    assert q4 = "00" severity failure;
+    assert q5 = "10" severity failure;
+    assert q6 = "10" severity failure;
+    assert q7 = "00" severity failure;
+    assert q8 = "10" severity failure;
+    assert q9 = "10" severity failure;
+
+    gate <= '1';
+    pulse;
+    assert q1 = "10" severity failure;
+    assert q2 = "11" severity failure;
+    assert q3 = "01" severity failure;
+    assert q4 = "10" severity failure;
+    assert q5 = "11" severity failure;
+    assert q6 = "01" severity failure;
+    assert q7 = "10" severity failure;
+    assert q8 = "11" severity failure;
+    assert q9 = "01" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue2237/tb_implicit_wide3.vhdl b/testsuite/synth/issue2237/tb_implicit_wide3.vhdl
new file mode 100644
index 000000000..0a374cdef
--- /dev/null
+++ b/testsuite/synth/issue2237/tb_implicit_wide3.vhdl
@@ -0,0 +1,136 @@
+entity tb_implicit_wide3 is
+end tb_implicit_wide3;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of tb_implicit_wide3 is
+  signal clk  : std_logic;
+  signal gate : std_logic;
+  signal d1   : std_logic_vector(1 downto 0);
+  signal q1   : std_logic_vector(1 downto 0);
+  signal q2   : std_logic_vector(1 downto 0);
+  signal q3   : std_logic_vector(1 downto 0);
+  signal d2   : unsigned(1 downto 0);
+  signal q4   : unsigned(1 downto 0);
+  signal q5   : unsigned(1 downto 0);
+  signal q6   : unsigned(1 downto 0);
+  signal d3   : signed(1 downto 0);
+  signal q7   : signed(1 downto 0);
+  signal q8   : signed(1 downto 0);
+  signal q9   : signed(1 downto 0);
+begin
+  dut: entity work.implicit_wide3
+    port map (
+      clk  => clk,
+      gate => gate,
+      d1   => d1,
+      q1   => q1,
+      q2   => q2,
+      q3   => q3,
+      d2   => d2,
+      q4   => q4,
+      q5   => q5,
+      q6   => q6,
+      d3   => d3,
+      q7   => q7,
+      q8   => q8,
+      q9   => q9);
+  
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    d1 <= "00";
+    d2 <= "00";
+    d3 <= "00";
+
+    gate <= '0';
+    pulse;
+    assert q1 = "11" severity failure;
+    assert q2 = "11" severity failure;
+    assert q3 = "11" severity failure;
+    assert q4 = "11" severity failure;
+    assert q5 = "11" severity failure;
+    assert q6 = "11" severity failure;
+    assert q7 = "11" severity failure;
+    assert q8 = "11" severity failure;
+    assert q9 = "11" severity failure;
+
+    gate <= '1';
+    pulse;
+    assert q1 = "11" severity failure;
+    assert q2 = "00" severity failure;
+    assert q3 = "00" severity failure;
+    assert q4 = "11" severity failure;
+    assert q5 = "00" severity failure;
+    assert q6 = "00" severity failure;
+    assert q7 = "11" severity failure;
+    assert q8 = "00" severity failure;
+    assert q9 = "00" severity failure;
+
+    d1 <= "01";
+    d2 <= "01";
+    d3 <= "01";
+
+    gate <= '0';
+    pulse;
+    assert q1 = "11" severity failure;
+    assert q2 = "10" severity failure;
+    assert q3 = "10" severity failure;
+    assert q4 = "11" severity failure;
+    assert q5 = "10" severity failure;
+    assert q6 = "10" severity failure;
+    assert q7 = "11" severity failure;
+    assert q8 = "10" severity failure;
+    assert q9 = "10" severity failure;
+
+    gate <= '1';
+    pulse;
+    assert q1 = "10" severity failure;
+    assert q2 = "00" severity failure;
+    assert q3 = "01" severity failure;
+    assert q4 = "10" severity failure;
+    assert q5 = "00" severity failure;
+    assert q6 = "01" severity failure;
+    assert q7 = "10" severity failure;
+    assert q8 = "00" severity failure;
+    assert q9 = "01" severity failure;
+
+    d1 <= "10";
+    d2 <= "10";
+    d3 <= "10";
+
+    gate <= '0';
+    pulse;
+    assert q1 = "11" severity failure;
+    assert q2 = "01" severity failure;
+    assert q3 = "01" severity failure;
+    assert q4 = "11" severity failure;
+    assert q5 = "01" severity failure;
+    assert q6 = "01" severity failure;
+    assert q7 = "11" severity failure;
+    assert q8 = "01" severity failure;
+    assert q9 = "01" severity failure;
+
+    gate <= '1';
+    pulse;
+    assert q1 = "01" severity failure;
+    assert q2 = "00" severity failure;
+    assert q3 = "10" severity failure;
+    assert q4 = "01" severity failure;
+    assert q5 = "00" severity failure;
+    assert q6 = "10" severity failure;
+    assert q7 = "01" severity failure;
+    assert q8 = "00" severity failure;
+    assert q9 = "10" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue2237/tb_implicit_wide4.vhdl b/testsuite/synth/issue2237/tb_implicit_wide4.vhdl
new file mode 100644
index 000000000..ac4be5208
--- /dev/null
+++ b/testsuite/synth/issue2237/tb_implicit_wide4.vhdl
@@ -0,0 +1,136 @@
+entity tb_implicit_wide4 is
+end tb_implicit_wide4;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of tb_implicit_wide4 is
+  signal clk  : std_logic;
+  signal gate : std_logic;
+  signal d1   : std_logic_vector(1 downto 0);
+  signal q1   : std_logic_vector(1 downto 0);
+  signal q2   : std_logic_vector(1 downto 0);
+  signal q3   : std_logic_vector(1 downto 0);
+  signal d2   : unsigned(1 downto 0);
+  signal q4   : unsigned(1 downto 0);
+  signal q5   : unsigned(1 downto 0);
+  signal q6   : unsigned(1 downto 0);
+  signal d3   : signed(1 downto 0);
+  signal q7   : signed(1 downto 0);
+  signal q8   : signed(1 downto 0);
+  signal q9   : signed(1 downto 0);
+begin
+  dut: entity work.implicit_wide4
+    port map (
+      clk  => clk,
+      gate => gate,
+      d1   => d1,
+      q1   => q1,
+      q2   => q2,
+      q3   => q3,
+      d2   => d2,
+      q4   => q4,
+      q5   => q5,
+      q6   => q6,
+      d3   => d3,
+      q7   => q7,
+      q8   => q8,
+      q9   => q9);
+  
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    d1 <= "00";
+    d2 <= "00";
+    d3 <= "00";
+
+    gate <= '0';
+    pulse;
+    assert q1 = "11" severity failure;
+    assert q2 = "11" severity failure;
+    assert q3 = "11" severity failure;
+    assert q4 = "11" severity failure;
+    assert q5 = "11" severity failure;
+    assert q6 = "11" severity failure;
+    assert q7 = "11" severity failure;
+    assert q8 = "11" severity failure;
+    assert q9 = "11" severity failure;
+
+    gate <= '1';
+    pulse;
+    assert q1 = "11" severity failure;
+    assert q2 = "00" severity failure;
+    assert q3 = "00" severity failure;
+    assert q4 = "11" severity failure;
+    assert q5 = "00" severity failure;
+    assert q6 = "00" severity failure;
+    assert q7 = "11" severity failure;
+    assert q8 = "00" severity failure;
+    assert q9 = "00" severity failure;
+
+    d1 <= "01";
+    d2 <= "01";
+    d3 <= "01";
+
+    gate <= '0';
+    pulse;
+    assert q1 = "11" severity failure;
+    assert q2 = "10" severity failure;
+    assert q3 = "10" severity failure;
+    assert q4 = "11" severity failure;
+    assert q5 = "10" severity failure;
+    assert q6 = "10" severity failure;
+    assert q7 = "11" severity failure;
+    assert q8 = "10" severity failure;
+    assert q9 = "10" severity failure;
+
+    gate <= '1';
+    pulse;
+    assert q1 = "10" severity failure;
+    assert q2 = "00" severity failure;
+    assert q3 = "01" severity failure;
+    assert q4 = "10" severity failure;
+    assert q5 = "00" severity failure;
+    assert q6 = "01" severity failure;
+    assert q7 = "10" severity failure;
+    assert q8 = "00" severity failure;
+    assert q9 = "01" severity failure;
+
+    d1 <= "10";
+    d2 <= "10";
+    d3 <= "10";
+
+    gate <= '0';
+    pulse;
+    assert q1 = "11" severity failure;
+    assert q2 = "01" severity failure;
+    assert q3 = "01" severity failure;
+    assert q4 = "11" severity failure;
+    assert q5 = "01" severity failure;
+    assert q6 = "01" severity failure;
+    assert q7 = "11" severity failure;
+    assert q8 = "01" severity failure;
+    assert q9 = "01" severity failure;
+
+    gate <= '1';
+    pulse;
+    assert q1 = "01" severity failure;
+    assert q2 = "00" severity failure;
+    assert q3 = "10" severity failure;
+    assert q4 = "01" severity failure;
+    assert q5 = "00" severity failure;
+    assert q6 = "10" severity failure;
+    assert q7 = "01" severity failure;
+    assert q8 = "00" severity failure;
+    assert q9 = "10" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue2237/testsuite.sh b/testsuite/synth/issue2237/testsuite.sh
new file mode 100755
index 000000000..72506c1b0
--- /dev/null
+++ b/testsuite/synth/issue2237/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+for t in implicit_wide implicit_wide2 implicit_wide3; do
+    synth_tb $t
+done
+
+echo "Test successful"