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author | Tristan Gingold <tgingold@free.fr> | 2022-08-14 21:55:05 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-08-14 21:55:05 +0200 |
commit | 6d4fad2cb725799d2c7834cd0918e4036905f24e (patch) | |
tree | 88aece00404d1d744ea3c2382639d8c5c2e201ca /testsuite/synth/issue2177/vlm5030_subcircuits.vhd | |
parent | 153fbf23a362bc56275a009670e3de65e82b7987 (diff) | |
download | ghdl-6d4fad2cb725799d2c7834cd0918e4036905f24e.tar.gz ghdl-6d4fad2cb725799d2c7834cd0918e4036905f24e.tar.bz2 ghdl-6d4fad2cb725799d2c7834cd0918e4036905f24e.zip |
testsuite/synth: add a test for #2177
Diffstat (limited to 'testsuite/synth/issue2177/vlm5030_subcircuits.vhd')
-rw-r--r-- | testsuite/synth/issue2177/vlm5030_subcircuits.vhd | 203 |
1 files changed, 203 insertions, 0 deletions
diff --git a/testsuite/synth/issue2177/vlm5030_subcircuits.vhd b/testsuite/synth/issue2177/vlm5030_subcircuits.vhd new file mode 100644 index 000000000..5e3da1a93 --- /dev/null +++ b/testsuite/synth/issue2177/vlm5030_subcircuits.vhd @@ -0,0 +1,203 @@ +---------------------------------------------------------------------- +-- VLM5030 +-- www.fpgaarcade.com +-- All rights reserved. +-- +-- admin@fpgaarcade.com +-- +-- This Source Code Form is subject to the terms of the Mozilla Public +-- License, v. 2.0. If a copy of the MPL was not distributed with this +-- file, You can obtain one at https://mozilla.org/MPL/2.0/. +---------------------------------------------------------------------- +-- +-- Copyright (c) 2021, Arnim Laeuger arnim.laeuger@gmx.net +-- All rights reserved. +-- + + +------------------------------------------------------------------------------- +-- SR-latch, synchronous to common clock +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity vlm5030_srlatch is + + port ( + i_clk : in std_logic; + i_res : in std_logic; + i_set : in std_logic; + o_q : out std_logic + ); + +end; + +architecture rtl of vlm5030_srlatch is + signal q : std_logic := '0'; +begin + + process (i_clk) + begin + if rising_edge(i_clk) then + if i_res = '1' then + q <= '0'; + elsif i_set = '1' then + q <= '1'; + end if; + end if; + end process; + + o_q <= q; + +end; + + +------------------------------------------------------------------------------- +-- SR-latch, synchronous to common clock, r_clk version +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +use work.clock_functions_pack.all; + +entity vlm5030_srlatchclk is + + port ( + i_clk : in r_clk; + i_res : in r_clk; + i_set : in r_clk; + o_q : out r_clk + ); + +end; + +architecture rtl of vlm5030_srlatchclk is + signal q : std_logic := '0'; +begin + + process (i_clk) + begin + if rising_edge(i_clk) then + if i_res.val = '1' then + q <= '0'; + elsif i_set.val = '1' then + q <= '1'; + end if; + end if; + end process; + + o_q <= (base => i_clk.base, + val => q, + rise => not q and i_set.val, + fall => q and i_res.val); + +end; + + +------------------------------------------------------------------------------- +-- vlm5030_delay +-- +-- Delay input signal by the specified number of clocks. +-- +-- NOTE: This is inertial delay. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use work.clock_functions_pack.all; + +entity vlm5030_delay is + + generic ( + g_numclks : integer := 3 + ); + port ( + i_clk : in r_clk; + i_in : in std_logic; + o_out : out std_logic + ); + +end; + +architecture rtl of vlm5030_delay is +begin + + delay_p : process (i_clk) + variable cnt : natural := 0; + variable inq : std_logic := '0'; + begin + if rising_edge(i_clk) then + if i_in /= inq then + cnt := g_numclks-2; + inq := i_in; + else + if cnt > 0 then + cnt := cnt - 1; + else + o_out <= i_in; + end if; + end if; + end if; + end process; + +end; + + +------------------------------------------------------------------------------- +-- vlm5030_delay_inv +-- +-- Invert input signal and delay falling edge of input. +-- The input's rising edge is not delayed. +-- +-- NOTE: This is inertial delay. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use work.clock_functions_pack.all; + +entity vlm5030_delay_inv is + + generic ( + g_numclks : integer := 3 + ); + port ( + i_clk : in r_clk; + i_in : in std_logic; + o_out : out std_logic + ); + +end; + +architecture rtl of vlm5030_delay_inv is + signal outq : std_logic; +begin + + delay_p : process (i_clk) + variable cnt : natural := 0; + variable inq : std_logic := '0'; + begin + if rising_edge(i_clk) then + if i_in /= inq then + cnt := g_numclks-2; + inq := i_in; + if i_in = '1' then + outq <= '1'; + end if; + else + if cnt > 0 then + cnt := cnt - 1; + else + outq <= i_in; + end if; + end if; + end if; + end process; + + o_out <= '0' when i_in = '1' else not outq; + +end; |