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authorTristan Gingold <tgingold@free.fr>2022-07-27 05:29:31 +0200
committerTristan Gingold <tgingold@free.fr>2022-07-27 05:29:31 +0200
commit14ce9c64ec5e662366fa1c6456283e0704f729f4 (patch)
treebb94309b894936109e4387997ec2f78f9166fd50 /testsuite/synth/issue2143/bug.vhdl
parentb6a5511c44066ff38b9efee0e3eaff0aa4dda973 (diff)
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testsuite/synth: add tests for #2143
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diff --git a/testsuite/synth/issue2143/bug.vhdl b/testsuite/synth/issue2143/bug.vhdl
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+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity bug is
+ port (
+ dummy : in std_ulogic
+ );
+end bug;
+
+architecture struct of bug is
+ type entry_t is record
+ a : std_ulogic;
+ end record;
+
+ type table_t is array (natural range<>, natural range<>) of entry_t;
+
+ function fun return table_t is
+ variable ret : table_t(0 to 7, 0 to 7);
+ begin
+ return ret;
+ end function;
+
+ constant table : table_t := fun;
+ constant entry : entry_t := table(0, 0);
+begin
+
+end architecture;