testsuite/synth: add tests for #2143

5 files changed, 102 insertions, 0 deletions

diff --git a/testsuite/synth/issue2143/bug.vhdl b/testsuite/synth/issue2143/bug.vhdl
new file mode 100644
index 000000000..19fdc2e35
--- /dev/null
+++ b/testsuite/synth/issue2143/bug.vhdl
@@ -0,0 +1,27 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity bug is
+	port (
+		dummy : in std_ulogic
+	);
+end bug;
+
+architecture struct of bug is
+	type entry_t is record
+		a : std_ulogic;
+	end record;
+
+	type table_t is array (natural range<>, natural range<>) of entry_t;
+
+	function fun return table_t is
+		variable ret : table_t(0 to 7, 0 to 7);
+	begin
+		return ret;
+	end function;
+
+	constant table : table_t := fun;
+	constant entry : entry_t := table(0, 0);
+begin
+
+end architecture;
diff --git a/testsuite/synth/issue2143/bug2.vhdl b/testsuite/synth/issue2143/bug2.vhdl
new file mode 100644
index 000000000..cf800ed4e
--- /dev/null
+++ b/testsuite/synth/issue2143/bug2.vhdl
@@ -0,0 +1,23 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity bug2 is
+	port (
+		dummy : in std_ulogic
+	);
+end bug2;
+
+architecture struct of bug2 is
+	type table_t is array (natural range<>, natural range<>) of std_ulogic;
+
+	function fun return table_t is
+		variable ret : table_t(0 to 7, 0 to 7);
+	begin
+		return ret;
+	end function;
+
+	constant table : table_t := fun;
+	constant entry : std_ulogic := table(0, 0);
+begin
+
+end architecture;
diff --git a/testsuite/synth/issue2143/repro1.vhdl b/testsuite/synth/issue2143/repro1.vhdl
new file mode 100644
index 000000000..c51baf62c
--- /dev/null
+++ b/testsuite/synth/issue2143/repro1.vhdl
@@ -0,0 +1,20 @@
+entity repro1 is
+end repro1;
+
+architecture struct of repro1 is
+	type entry_t is record
+		a : bit;
+	end record;
+
+	type table_t is array (natural range<>, natural range<>) of entry_t;
+
+	function fun return table_t is
+		variable ret : table_t(0 to 7, 0 to 7);
+	begin
+		return ret;
+	end function;
+
+	constant entry : entry_t := fun(0, 0);
+begin
+
+end architecture;
diff --git a/testsuite/synth/issue2143/repro2.vhdl b/testsuite/synth/issue2143/repro2.vhdl
new file mode 100644
index 000000000..3e7213dee
--- /dev/null
+++ b/testsuite/synth/issue2143/repro2.vhdl
@@ -0,0 +1,22 @@
+entity repro2 is
+  port (clk : bit;
+        o : out bit);
+end;
+
+architecture struct of repro2 is
+	type entry_t is record
+		a : bit;
+	end record;
+
+	type table_t is array (natural range<>, natural range<>) of entry_t;
+
+	function fun return table_t is
+		variable ret : table_t(0 to 7, 0 to 7);
+	begin
+		return ret;
+	end function;
+
+        constant table : table_t := fun;
+begin
+  o <= table(0,0).a when clk = '1' else '0';
+end architecture;
diff --git a/testsuite/synth/issue2143/testsuite.sh b/testsuite/synth/issue2143/testsuite.sh
new file mode 100755
index 000000000..de5f5d8d0
--- /dev/null
+++ b/testsuite/synth/issue2143/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_only repro1
+synth_only repro2
+synth_only bug
+synth_only bug2
+
+echo "Test successful"