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authorTristan Gingold <tgingold@free.fr>2023-01-10 18:51:41 +0100
committerTristan Gingold <tgingold@free.fr>2023-01-10 21:46:59 +0100
commit4ded79ccbbafe357dcb21ddb7cdaf12f831e967c (patch)
tree152ec5c424334faf6ed2728fd85c32691a4760fd /testsuite/synth/issue1926/ecp5pll.vhdl
parent26ed24d29ba32865be97ff1023d6442021a4db60 (diff)
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simul: enable all debug features during elaboration
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