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author | Tristan Gingold <tgingold@free.fr> | 2020-04-18 07:27:26 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-04-18 07:27:26 +0200 |
commit | 9e0de040d782b0ec85e03a359319901c32663e33 (patch) | |
tree | f603ee391624ba186fe42f17afe46a800820aeec /testsuite/synth/issue1241/top.vhdl | |
parent | c261402a951b58e9560a69b9d9822285e7197506 (diff) | |
download | ghdl-9e0de040d782b0ec85e03a359319901c32663e33.tar.gz ghdl-9e0de040d782b0ec85e03a359319901c32663e33.tar.bz2 ghdl-9e0de040d782b0ec85e03a359319901c32663e33.zip |
testsuite/synth: add a test for #1241
Diffstat (limited to 'testsuite/synth/issue1241/top.vhdl')
-rw-r--r-- | testsuite/synth/issue1241/top.vhdl | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/testsuite/synth/issue1241/top.vhdl b/testsuite/synth/issue1241/top.vhdl new file mode 100644 index 000000000..c45aff954 --- /dev/null +++ b/testsuite/synth/issue1241/top.vhdl @@ -0,0 +1,28 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity top is + port( + sel : in unsigned(1 downto 0); + data : in std_logic_vector(3 downto 0); + q : out std_logic + ); +end entity; + +architecture arch of top is + type record_t is record + x : std_logic_vector(1 downto 0); + y : std_logic_vector(1 downto 0); + end record; + + type array_t is array (0 to 1) of record_t; + signal a : array_t; +begin + a <= (("11", data(1 downto 0)), ("11", data(3 downto 2))); + q <= a(to_integer(sel(1 downto 1))).y(to_integer(sel(0 downto 0))); +end architecture; + +-- A0 A1 +-- Y1 Y0 X1 X0 Y1 Y0 X1 X0 +-- A + sel1*4 + 2 + sel0*1 |