From 9e0de040d782b0ec85e03a359319901c32663e33 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 18 Apr 2020 07:27:26 +0200
Subject: testsuite/synth: add a test for #1241

---
 testsuite/synth/issue1241/top.vhdl | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 testsuite/synth/issue1241/top.vhdl

(limited to 'testsuite/synth/issue1241/top.vhdl')

diff --git a/testsuite/synth/issue1241/top.vhdl b/testsuite/synth/issue1241/top.vhdl
new file mode 100644
index 000000000..c45aff954
--- /dev/null
+++ b/testsuite/synth/issue1241/top.vhdl
@@ -0,0 +1,28 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity top is
+	port(
+		sel : in unsigned(1 downto 0);
+		data : in std_logic_vector(3 downto 0);
+		q : out std_logic
+	);
+end entity;
+
+architecture arch of top is
+	type record_t is record
+		x : std_logic_vector(1 downto 0);
+		y : std_logic_vector(1 downto 0);
+	end record;
+
+	type array_t is array (0 to 1) of record_t;
+	signal a : array_t;
+begin
+	a <= (("11", data(1 downto 0)), ("11", data(3 downto 2)));
+	q <= a(to_integer(sel(1 downto 1))).y(to_integer(sel(0 downto 0)));
+end architecture;
+
+--  A0             A1
+--    Y1 Y0 X1 X0      Y1 Y0 X1 X0
+--  A + sel1*4 + 2 + sel0*1
-- 
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