testsuite/synth: add tests for #1163

4 files changed, 114 insertions, 0 deletions

diff --git a/testsuite/synth/issue1163/bug.vhdl b/testsuite/synth/issue1163/bug.vhdl
new file mode 100644
index 000000000..1e50c5f93
--- /dev/null
+++ b/testsuite/synth/issue1163/bug.vhdl
@@ -0,0 +1,36 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity bug is
+	generic(
+		W    : positive := 4;
+		N    : positive := 4
+	);
+	port(
+		clk     :  in std_ulogic;
+		reset_n :  in std_ulogic
+	);
+end bug;
+
+architecture behav of bug is
+	type queue_info_t is record
+		dummy : integer range 0 to W-1;
+		strb  : std_ulogic_vector(W-1 downto 0);
+	end record;
+
+	type queues_t is array (0 to N-1) of queue_info_t;
+	signal queues : queues_t;
+begin
+
+	process(clk, reset_n)
+		variable index : integer range 0 to N-1;
+	begin
+		if reset_n = '0' then
+		elsif rising_edge(clk) then
+			for i in 0 to W-1 loop
+				queues(index).strb(i) <= '0';
+			end loop;
+		end if;
+	end process;
+end architecture;
diff --git a/testsuite/synth/issue1163/bug2.vhdl b/testsuite/synth/issue1163/bug2.vhdl
new file mode 100644
index 000000000..d355fbed6
--- /dev/null
+++ b/testsuite/synth/issue1163/bug2.vhdl
@@ -0,0 +1,41 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity bug2 is
+	generic(
+		W    : positive := 4;
+		N    : positive := 4
+	);
+	port(
+		clk     :  in std_ulogic;
+		reset_n :  in std_ulogic;
+                o : out std_ulogic
+	);
+end bug2;
+
+architecture behav of bug2 is
+	type queue_info_t is record
+		dummy : integer range 0 to W-1;
+		strb  : std_ulogic_vector(W-1 downto 0);
+	end record;
+
+	type queues_t is array (0 to N-1) of queue_info_t;
+	signal queues : queues_t;
+begin
+
+	process(clk, reset_n)
+		variable index : integer range 0 to N-1;
+	begin
+          if reset_n = '0' then
+            index := 0;
+          elsif rising_edge(clk) then
+            for i in 0 to W-1 loop
+              queues(index).strb(i) <= '0';
+            end loop;
+            index := (index + 1) mod N;
+          end if;
+	end process;
+
+        o <=  queues (0).strb (0);
+end architecture;
diff --git a/testsuite/synth/issue1163/bug3.vhdl b/testsuite/synth/issue1163/bug3.vhdl
new file mode 100644
index 000000000..071972d37
--- /dev/null
+++ b/testsuite/synth/issue1163/bug3.vhdl
@@ -0,0 +1,27 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity bug is
+    port(index : in integer range 0 to 1);
+end bug;
+
+architecture behav of bug is
+
+    type foobar is record
+        foo : std_logic;
+        bar : std_logic_vector(1 downto 0);
+    end record;
+
+    -- Changing the order works:
+    --type foobar is record
+    --    bar : std_logic_vector(1 downto 0);
+    --    foo : std_logic;
+    --end record;
+
+    type foobar_array is array (0 to 1) of foobar;
+
+    signal s_foobar : foobar_array;
+begin
+    s_foobar(index).bar(0) <= '0';
+end architecture;
diff --git a/testsuite/synth/issue1163/testsuite.sh b/testsuite/synth/issue1163/testsuite.sh
new file mode 100755
index 000000000..814df991c
--- /dev/null
+++ b/testsuite/synth/issue1163/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for f in bug bug2 bug3; do
+  synth_analyze $f
+  clean
+done
+
+echo "Test successful"