testsuite/synth: avoid use of verilog identifiers

1 files changed, 2 insertions, 2 deletions

diff --git a/testsuite/synth/issue1107/unconnected.vhdl b/testsuite/synth/issue1107/unconnected.vhdl
index 0c7886a24..d8dcd2a10 100644
--- a/testsuite/synth/issue1107/unconnected.vhdl
+++ b/testsuite/synth/issue1107/unconnected.vhdl
@@ -4,12 +4,12 @@ use ieee.std_logic_1164.all;
 
 entity unconnected is
   port (
-    output: out std_logic
+    outp: out std_logic
     );
 end entity;
 
 architecture arch of unconnected is
   signal no_value: std_logic;
 begin
-  output <= no_value;
+  outp <= no_value;
 end;