From 0416c788cd9aecd1a2bc8e7a517606d181d99921 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 28 Nov 2021 18:15:29 +0100
Subject: testsuite/synth: avoid use of verilog identifiers

---
 testsuite/synth/issue1107/unconnected.vhdl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'testsuite/synth/issue1107')

diff --git a/testsuite/synth/issue1107/unconnected.vhdl b/testsuite/synth/issue1107/unconnected.vhdl
index 0c7886a24..d8dcd2a10 100644
--- a/testsuite/synth/issue1107/unconnected.vhdl
+++ b/testsuite/synth/issue1107/unconnected.vhdl
@@ -4,12 +4,12 @@ use ieee.std_logic_1164.all;
 
 entity unconnected is
   port (
-    output: out std_logic
+    outp: out std_logic
     );
 end entity;
 
 architecture arch of unconnected is
   signal no_value: std_logic;
 begin
-  output <= no_value;
+  outp <= no_value;
 end;
-- 
cgit v1.2.3