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author | Tristan Gingold <tgingold@free.fr> | 2021-11-28 18:15:29 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-11-28 18:15:29 +0100 |
commit | 0416c788cd9aecd1a2bc8e7a517606d181d99921 (patch) | |
tree | 4c3a8886cca8fb996f42118696e9369656018084 /testsuite/synth/issue1107/unconnected.vhdl | |
parent | c7d32abe6f8108c0e7af6eea5d546be2bd83b704 (diff) | |
download | ghdl-0416c788cd9aecd1a2bc8e7a517606d181d99921.tar.gz ghdl-0416c788cd9aecd1a2bc8e7a517606d181d99921.tar.bz2 ghdl-0416c788cd9aecd1a2bc8e7a517606d181d99921.zip |
testsuite/synth: avoid use of verilog identifiers
Diffstat (limited to 'testsuite/synth/issue1107/unconnected.vhdl')
-rw-r--r-- | testsuite/synth/issue1107/unconnected.vhdl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/testsuite/synth/issue1107/unconnected.vhdl b/testsuite/synth/issue1107/unconnected.vhdl index 0c7886a24..d8dcd2a10 100644 --- a/testsuite/synth/issue1107/unconnected.vhdl +++ b/testsuite/synth/issue1107/unconnected.vhdl @@ -4,12 +4,12 @@ use ieee.std_logic_1164.all; entity unconnected is port ( - output: out std_logic + outp: out std_logic ); end entity; architecture arch of unconnected is signal no_value: std_logic; begin - output <= no_value; + outp <= no_value; end; |