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author | Tristan Gingold <tgingold@free.fr> | 2023-01-10 18:51:41 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2023-01-10 21:46:59 +0100 |
commit | 4ded79ccbbafe357dcb21ddb7cdaf12f831e967c (patch) | |
tree | 152ec5c424334faf6ed2728fd85c32691a4760fd /testsuite/synth/issue1069/tb_ram41.vhdl | |
parent | 26ed24d29ba32865be97ff1023d6442021a4db60 (diff) | |
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simul: enable all debug features during elaboration
Diffstat (limited to 'testsuite/synth/issue1069/tb_ram41.vhdl')
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