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authorTristan Gingold <tgingold@free.fr>2019-11-12 20:40:47 +0100
committerTristan Gingold <tgingold@free.fr>2019-11-12 20:40:47 +0100
commit1b2a14b3f7cf9adbd600e36b1a581dc137316af7 (patch)
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parent329df90440cc4bf53229afe16f84ec4caa50e8bf (diff)
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testsuite/synth: add testcase for #1008
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diff --git a/testsuite/synth/issue1008/test.vhdl b/testsuite/synth/issue1008/test.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test is
+ port(
+ addr_in : in std_logic_vector(11 downto 0);
+ dat_out : out std_logic_vector(63 downto 0)
+ );
+end entity test;
+
+architecture behaviour of test is
+ type ram_t is array(0 to (4096 / 8) - 1) of std_logic_vector(63 downto 0);
+ signal memory : ram_t := (others => (others => '0'));
+ signal idx : natural := 0;
+begin
+ idx <= to_integer(unsigned(addr_in(11 downto 3)));
+ dat_out <= memory(idx);
+end architecture behaviour;