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author | Tristan Gingold <tgingold@free.fr> | 2019-11-12 20:40:47 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-11-12 20:40:47 +0100 |
commit | 1b2a14b3f7cf9adbd600e36b1a581dc137316af7 (patch) | |
tree | fd57b003373bb1b181b6db32842b3fd4f54a6f39 /testsuite/synth/issue1008/test.vhdl | |
parent | 329df90440cc4bf53229afe16f84ec4caa50e8bf (diff) | |
download | ghdl-1b2a14b3f7cf9adbd600e36b1a581dc137316af7.tar.gz ghdl-1b2a14b3f7cf9adbd600e36b1a581dc137316af7.tar.bz2 ghdl-1b2a14b3f7cf9adbd600e36b1a581dc137316af7.zip |
testsuite/synth: add testcase for #1008
Diffstat (limited to 'testsuite/synth/issue1008/test.vhdl')
-rw-r--r-- | testsuite/synth/issue1008/test.vhdl | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/testsuite/synth/issue1008/test.vhdl b/testsuite/synth/issue1008/test.vhdl new file mode 100644 index 000000000..b84ebb3af --- /dev/null +++ b/testsuite/synth/issue1008/test.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity test is + port( + addr_in : in std_logic_vector(11 downto 0); + dat_out : out std_logic_vector(63 downto 0) + ); +end entity test; + +architecture behaviour of test is + type ram_t is array(0 to (4096 / 8) - 1) of std_logic_vector(63 downto 0); + signal memory : ram_t := (others => (others => '0')); + signal idx : natural := 0; +begin + idx <= to_integer(unsigned(addr_in(11 downto 3))); + dat_out <= memory(idx); +end architecture behaviour; |