testsuite/synth: add testcase for #1008

3 files changed, 48 insertions, 0 deletions

diff --git a/testsuite/synth/issue1008/test.vhdl b/testsuite/synth/issue1008/test.vhdl
new file mode 100644
index 000000000..b84ebb3af
--- /dev/null
+++ b/testsuite/synth/issue1008/test.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test is
+    port(
+         addr_in : in std_logic_vector(11 downto 0);
+         dat_out : out std_logic_vector(63 downto 0)
+         );
+end entity test;
+
+architecture behaviour of test is
+    type ram_t is array(0 to (4096 / 8) - 1) of std_logic_vector(63 downto 0);
+    signal memory : ram_t := (others => (others => '0'));
+    signal idx : natural := 0;
+begin
+    idx <= to_integer(unsigned(addr_in(11 downto 3)));
+    dat_out <= memory(idx);
+end architecture behaviour;
diff --git a/testsuite/synth/issue1008/test_orig.vhdl b/testsuite/synth/issue1008/test_orig.vhdl
new file mode 100644
index 000000000..c568a0530
--- /dev/null
+++ b/testsuite/synth/issue1008/test_orig.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test is
+    port(
+         addr_in : in std_logic_vector(11 downto 0);
+         dat_out : out std_ulogic_vector(63 downto 0)
+         );
+end entity test;
+
+architecture behaviour of test is
+    type ram_t is array(0 to (4096 / 8) - 1) of std_logic_vector(63 downto 0);
+    signal memory : ram_t := (others => (others => '0'));
+begin
+    dat_out <= memory(to_integer(unsigned(addr_in(11 downto 3))));
+end architecture behaviour;
diff --git a/testsuite/synth/issue1008/testsuite.sh b/testsuite/synth/issue1008/testsuite.sh
new file mode 100755
index 000000000..a57680e9c
--- /dev/null
+++ b/testsuite/synth/issue1008/testsuite.sh
@@ -0,0 +1,12 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+for t in test test_orig; do
+    synth -de $t.vhdl -e > syn_$t.vhdl
+    analyze syn_$t.vhdl
+    clean
+done
+
+echo "Test successful"