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authorTristan Gingold <tgingold@free.fr>2019-10-31 18:28:53 +0100
committerTristan Gingold <tgingold@free.fr>2019-10-31 18:28:53 +0100
commit6aa790b8d8ec7f3afa20fec929acaabb48ed8ca8 (patch)
treedb5160491bbf6f91be1c5c553be7ef1ebe10f69b /testsuite/synth/fsm03/assert4.psl
parent5790c35aaa4e69e421367850e59cd676f1c54787 (diff)
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testsuite/synth: add testcase for psl.
Diffstat (limited to 'testsuite/synth/fsm03/assert4.psl')
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diff --git a/testsuite/synth/fsm03/assert4.psl b/testsuite/synth/fsm03/assert4.psl
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+vunit assert3 (ent)
+{
+ default clock is rising_edge(clk);
+ function get_nval (v : std_logic) return std_logic is
+ begin
+ return not v;
+ end get_nval;
+ -- signal nval : std_logic;
+ my_cond: assert always {get_nval (val); req} |=> eventually! ack;
+}