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authorTristan Gingold <tgingold@free.fr>2019-10-08 18:44:34 +0200
committerTristan Gingold <tgingold@free.fr>2019-10-08 18:44:34 +0200
commit7119ed0eee11707dcfc6ab023fdf1f72783b35bd (patch)
treecdf72b5d0538f186d391e6cdd852c4f2d0859b9e /testsuite/synth/dispvhdl01/tb_vhd01.vhdl
parent0a3ca95575c7c5d3c153ec2de271613c228124a8 (diff)
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testsuite/synth: add a test.
Diffstat (limited to 'testsuite/synth/dispvhdl01/tb_vhd01.vhdl')
-rw-r--r--testsuite/synth/dispvhdl01/tb_vhd01.vhdl26
1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/synth/dispvhdl01/tb_vhd01.vhdl b/testsuite/synth/dispvhdl01/tb_vhd01.vhdl
new file mode 100644
index 000000000..6f2e1ec9b
--- /dev/null
+++ b/testsuite/synth/dispvhdl01/tb_vhd01.vhdl
@@ -0,0 +1,26 @@
+entity tb_vhd01 is
+end tb_vhd01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.pkg.all;
+
+architecture behav of tb_vhd01 is
+ signal i1, o1 : std_logic_vector(1 to 1);
+begin
+ dut: entity work.vhd01
+ port map (i1 => i1, o1 => o1);
+
+ process
+ begin
+ i1 <= "1";
+ wait for 1 ns;
+ assert o1 = "1" severity failure;
+
+ i1 <= "0";
+ wait for 1 ns;
+ assert o1 = "0" severity failure;
+
+ wait;
+ end process;
+end behav;