4 files changed, 63 insertions, 0 deletions
diff --git a/testsuite/synth/dispvhdl01/pkg.vhdl b/testsuite/synth/dispvhdl01/pkg.vhdl
new file mode 100644
index 000000000..592226f79
--- /dev/null
+++ b/testsuite/synth/dispvhdl01/pkg.vhdl
@@ -0,0 +1,8 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package pkg is
+  type myrec is record
+     b : std_logic;
+  end record;
+end pkg;
diff --git a/testsuite/synth/dispvhdl01/tb_vhd01.vhdl b/testsuite/synth/dispvhdl01/tb_vhd01.vhdl
new file mode 100644
index 000000000..6f2e1ec9b
--- /dev/null
+++ b/testsuite/synth/dispvhdl01/tb_vhd01.vhdl
@@ -0,0 +1,26 @@
+entity tb_vhd01 is
+end tb_vhd01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.pkg.all;
+
+architecture behav of tb_vhd01 is
+  signal i1, o1 : std_logic_vector(1 to 1);
+begin
+  dut: entity work.vhd01
+    port map (i1 => i1, o1 => o1);
+
+  process
+  begin
+    i1 <= "1";
+    wait for 1 ns;
+    assert o1 = "1" severity failure;
+
+    i1 <= "0";
+    wait for 1 ns;
+    assert o1 = "0" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dispvhdl01/testsuite.sh b/testsuite/synth/dispvhdl01/testsuite.sh
new file mode 100755
index 000000000..4c93e7067
--- /dev/null
+++ b/testsuite/synth/dispvhdl01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in vhd01; do
+    analyze pkg.vhdl $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth pkg.vhdl $t.vhdl -e $t > syn_$t.vhdl
+    analyze pkg.vhdl syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"
diff --git a/testsuite/synth/dispvhdl01/vhd01.vhdl b/testsuite/synth/dispvhdl01/vhd01.vhdl
new file mode 100644
index 000000000..89b3cc3a2
--- /dev/null
+++ b/testsuite/synth/dispvhdl01/vhd01.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use work.pkg.all;
+
+entity vhd01 is
+  port (i1 : std_logic_vector (1 to 1);
+        o1 : out std_logic_vector (1 to 1));
+end vhd01;
+
+architecture behav of vhd01 is
+begin
+  o1 <= i1;
+end behav;