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author | Tristan Gingold <tgingold@free.fr> | 2020-05-03 16:57:41 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-05-04 19:04:08 +0200 |
commit | d7f364c707c2767743150d92eff0fab3ddd58ceb (patch) | |
tree | aba70094e890fca53d0c6641e077dfbb936967b8 /testsuite/synth/case02/case03.vhdl | |
parent | 3629ed753e2a432d100b54bc94473ada803dc43c (diff) | |
download | ghdl-d7f364c707c2767743150d92eff0fab3ddd58ceb.tar.gz ghdl-d7f364c707c2767743150d92eff0fab3ddd58ceb.tar.bz2 ghdl-d7f364c707c2767743150d92eff0fab3ddd58ceb.zip |
testsuite/synth: add a test for previous commits.
Diffstat (limited to 'testsuite/synth/case02/case03.vhdl')
-rw-r--r-- | testsuite/synth/case02/case03.vhdl | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/testsuite/synth/case02/case03.vhdl b/testsuite/synth/case02/case03.vhdl new file mode 100644 index 000000000..6e7a8182f --- /dev/null +++ b/testsuite/synth/case02/case03.vhdl @@ -0,0 +1,44 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity case03 is + port ( + clk : in std_logic; + opc : in std_logic_vector (2 downto 0); + arg : in std_logic_vector (7 downto 0); + res : out std_logic_vector (7 downto 0); + par : out std_logic); +end case03; + +architecture behav of case03 is + signal result : std_logic_vector(7 downto 0); + signal parity : std_logic; +begin + process (clk) + begin + if rising_edge(clk) then + res <= result; + par <= parity; + end if; + end process; + + op : process (opc, arg) + variable t : std_logic_vector(7 downto 0); + variable p : std_logic; + begin + p := '0'; + case opc is + when "000" | "001" | "010" | "011" => + t := not arg; + + for i in t'range loop + p := p xor t(i); + end loop; + when others => + t := arg; + end case; + result <= t; + parity <= p; + end process; +end behav; + |