testsuite/synth: add a test for previous commits.

3 files changed, 92 insertions, 9 deletions

diff --git a/testsuite/synth/case02/case03.vhdl b/testsuite/synth/case02/case03.vhdl
new file mode 100644
index 000000000..6e7a8182f
--- /dev/null
+++ b/testsuite/synth/case02/case03.vhdl
@@ -0,0 +1,44 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity case03 is
+	port (
+		clk : in std_logic;
+		opc : in std_logic_vector (2 downto 0);
+		arg : in std_logic_vector (7 downto 0);
+		res : out std_logic_vector (7 downto 0);
+		par : out std_logic);
+end case03;
+
+architecture behav of case03 is
+  signal result : std_logic_vector(7 downto 0);
+  signal parity : std_logic;
+begin
+	process (clk)
+	begin
+		if rising_edge(clk) then
+		  res <= result;
+		  par <= parity;
+		end if;
+	end process;
+
+	op : process (opc, arg)
+		variable t : std_logic_vector(7 downto 0);
+		variable p : std_logic;
+	begin
+	  p := '0';
+	  case opc is
+		when "000" | "001" | "010" | "011" =>
+		  t := not arg;
+
+		  for i in t'range loop
+			p := p xor t(i);
+		  end loop;
+		when others =>
+		  t := arg;
+	  end case;
+	  result <= t;
+	  parity <= p;
+	end process;
+end behav;
+
diff --git a/testsuite/synth/case02/tb_case03.vhdl b/testsuite/synth/case02/tb_case03.vhdl
new file mode 100644
index 000000000..6988b1ca1
--- /dev/null
+++ b/testsuite/synth/case02/tb_case03.vhdl
@@ -0,0 +1,46 @@
+entity tb_case03 is
+end tb_case03;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_case03 is
+  signal clk : std_logic;
+  signal opc : std_logic_vector (2 downto 0);
+  signal arg : std_logic_vector (7 downto 0);
+  signal res : std_logic_vector (7 downto 0);
+  signal par : std_logic;
+begin
+  dut: entity work.case03
+    port map (clk, opc, arg, res, par);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    opc <= "000";
+    arg <= x"45";
+    pulse;
+    assert res = x"ba" severity failure;
+    assert par = '1' severity failure;
+
+    opc <= "010";
+    arg <= x"55";
+    pulse;
+    assert res = x"aa" severity failure;
+    assert par = '0' severity failure;
+
+    opc <= "110";
+    arg <= x"57";
+    pulse;
+    assert res = x"57" severity failure;
+    assert par = '0' severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/case02/testsuite.sh b/testsuite/synth/case02/testsuite.sh
index ecb19a503..899e0bfcf 100755
--- a/testsuite/synth/case02/testsuite.sh
+++ b/testsuite/synth/case02/testsuite.sh
@@ -2,15 +2,8 @@
 
 . ../../testenv.sh
 
-for t in case01 case02; do
-    analyze $t.vhdl tb_$t.vhdl
-    elab_simulate tb_$t
-    clean
-
-    synth $t.vhdl -e $t > syn_$t.vhdl
-    analyze syn_$t.vhdl tb_$t.vhdl
-    elab_simulate tb_$t
-    clean
+for t in case01 case02 case03; do
+    synth_tb $t
 done
 
 echo "Test successful"