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authorTristan Gingold <tgingold@free.fr>2019-10-14 06:49:23 +0200
committerTristan Gingold <tgingold@free.fr>2019-10-14 06:49:23 +0200
commitd37ba8b009f0a8954bfcf37720f6c3f13038ed63 (patch)
treefd0f496af046534d6f3da03b8dbb6aad46f20266 /testsuite/synth/asgn01/asgn08.vhdl
parent8603cf148413f4e0c0cdcfd61dea2ac7f37b6bc0 (diff)
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testsuite/synth: add testcase for previous commit.
Diffstat (limited to 'testsuite/synth/asgn01/asgn08.vhdl')
-rw-r--r--testsuite/synth/asgn01/asgn08.vhdl27
1 files changed, 27 insertions, 0 deletions
diff --git a/testsuite/synth/asgn01/asgn08.vhdl b/testsuite/synth/asgn01/asgn08.vhdl
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index 000000000..925afbce1
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+++ b/testsuite/synth/asgn01/asgn08.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity asgn08 is
+ port (clk : std_logic;
+ ce : std_logic;
+ s0 : std_logic;
+ r : out std_logic_vector (65 downto 0));
+end asgn08;
+
+architecture behav of asgn08 is
+begin
+ r (0) <= '1';
+
+ process (clk) is
+ begin
+ if rising_edge(clk) and ce = '1' then
+ if s0 = '1' then
+ r (64 downto 1) <= x"ffff_eeee_dddd_cccc";
+ r (65) <= '1';
+ else
+ r (8 downto 5) <= x"7";
+ r (65) <= '0';
+ end if;
+ end if;
+ end process;
+end behav;