testsuite/synth: add testcase for previous commit.

3 files changed, 80 insertions, 1 deletions

diff --git a/testsuite/synth/asgn01/asgn08.vhdl b/testsuite/synth/asgn01/asgn08.vhdl
new file mode 100644
index 000000000..925afbce1
--- /dev/null
+++ b/testsuite/synth/asgn01/asgn08.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity asgn08 is
+  port (clk : std_logic;
+        ce : std_logic;
+        s0 : std_logic;
+        r : out std_logic_vector (65 downto 0));
+end asgn08;
+
+architecture behav of asgn08 is
+begin
+  r (0) <= '1';
+
+  process (clk) is
+  begin
+    if rising_edge(clk) and ce = '1' then
+      if s0 = '1' then
+        r (64 downto 1) <= x"ffff_eeee_dddd_cccc";
+        r (65) <= '1';
+      else
+        r (8 downto 5) <= x"7";
+        r (65) <= '0';
+      end if;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/asgn01/tb_asgn08.vhdl b/testsuite/synth/asgn01/tb_asgn08.vhdl
new file mode 100644
index 000000000..470c71893
--- /dev/null
+++ b/testsuite/synth/asgn01/tb_asgn08.vhdl
@@ -0,0 +1,52 @@
+entity tb_asgn08 is
+end tb_asgn08;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_asgn08 is
+  signal s0 : std_logic;
+  signal clk : std_logic;
+  signal ce : std_logic;
+  signal r  : std_logic_vector (65 downto 0);
+begin
+  dut: entity work.asgn08
+    port map (clk => clk, ce => ce, s0 => s0, r => r);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    s0 <= '0';
+    ce <= '1';
+    pulse;
+    assert r (0) = '1' severity failure;
+    assert r (65) = '0' severity failure;
+
+    s0 <= '1';
+    pulse;
+    assert r (0) = '1' severity failure;
+    assert r (64 downto 1) = x"ffff_eeee_dddd_cccc" severity failure;
+    assert r (65) = '1' severity failure;
+
+    s0 <= '0';
+    ce <= '0';
+    pulse;
+    assert r (0) = '1' severity failure;
+    assert r (64 downto 1) = x"ffff_eeee_dddd_cccc" severity failure;
+    assert r (65) = '1' severity failure;
+
+    ce <= '1';
+    pulse;
+    assert r (0) = '1' severity failure;
+    assert r (64 downto 1) = x"ffff_eeee_dddd_cc7c" severity failure;
+    assert r (65) = '0' severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/asgn01/testsuite.sh b/testsuite/synth/asgn01/testsuite.sh
index d45c0c3bd..ad298ced7 100755
--- a/testsuite/synth/asgn01/testsuite.sh
+++ b/testsuite/synth/asgn01/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in asgn01 asgn02 asgn03 asgn04 asgn05 asgn06 asgn07 arr04; do
+for t in asgn01 asgn02 asgn03 asgn04 asgn05 asgn06 asgn07 asgn08 arr04; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean