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author | Tristan Gingold <tgingold@free.fr> | 2019-08-31 05:48:05 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-08-31 06:25:52 +0200 |
commit | a14e0e60f448526f6ee4dc2bb2a524a8cd324f6f (patch) | |
tree | 7c4c011375a2f2851f5cdf25743e279f66e28776 /testsuite/synth/asgn01/asgn05.vhdl | |
parent | 88942b924c92f2f90418706718b1bec3d38af007 (diff) | |
download | ghdl-a14e0e60f448526f6ee4dc2bb2a524a8cd324f6f.tar.gz ghdl-a14e0e60f448526f6ee4dc2bb2a524a8cd324f6f.tar.bz2 ghdl-a14e0e60f448526f6ee4dc2bb2a524a8cd324f6f.zip |
[PATCH] synth-environment: fix thinkos.
Diffstat (limited to 'testsuite/synth/asgn01/asgn05.vhdl')
-rw-r--r-- | testsuite/synth/asgn01/asgn05.vhdl | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/testsuite/synth/asgn01/asgn05.vhdl b/testsuite/synth/asgn01/asgn05.vhdl new file mode 100644 index 000000000..90614d159 --- /dev/null +++ b/testsuite/synth/asgn01/asgn05.vhdl @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity asgn05 is + port (s0 : std_logic; + s1 : std_logic; + r : out std_logic_vector (5 downto 0)); +end asgn05; + +architecture behav of asgn05 is +begin + process (s0, s1) is + begin + r <= "000000"; + if s0 = '1' then + r (1) <= '1'; + r (3) <= '1'; + r (4 downto 2) <= "101"; + end if; + end process; +end behav; |