[PATCH] synth-environment: fix thinkos.

7 files changed, 174 insertions, 1 deletions

diff --git a/testsuite/synth/asgn01/asgn03.vhdl b/testsuite/synth/asgn01/asgn03.vhdl
new file mode 100644
index 000000000..0b341c8c6
--- /dev/null
+++ b/testsuite/synth/asgn01/asgn03.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity asgn03 is
+  port (s0 : std_logic;
+        s1 : std_logic;
+        r : out std_logic_vector (2 downto 0));
+end asgn03;
+
+architecture behav of asgn03 is
+begin
+  process (s0, s1) is
+  begin
+    r <= "000";
+    if s0 = '1' then
+      r (1) <= '1';
+      if s1 = '1' then
+        --r(1 downto 0) <= "01";
+        r(0) <= '1';
+      end if;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/asgn01/asgn04.vhdl b/testsuite/synth/asgn01/asgn04.vhdl
new file mode 100644
index 000000000..0c9149aa4
--- /dev/null
+++ b/testsuite/synth/asgn01/asgn04.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity asgn04 is
+  port (s0 : std_logic;
+        s1 : std_logic;
+        r : out std_logic_vector (2 downto 0));
+end asgn04;
+
+architecture behav of asgn04 is
+begin
+  process (s0, s1) is
+  begin
+    r <= "000";
+    if s0 = '1' then
+      r (1) <= '1';
+      if s1 = '1' then
+        r(1 downto 0) <= "01";
+      end if;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/asgn01/asgn05.vhdl b/testsuite/synth/asgn01/asgn05.vhdl
new file mode 100644
index 000000000..90614d159
--- /dev/null
+++ b/testsuite/synth/asgn01/asgn05.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity asgn05 is
+  port (s0 : std_logic;
+        s1 : std_logic;
+        r : out std_logic_vector (5 downto 0));
+end asgn05;
+
+architecture behav of asgn05 is
+begin
+  process (s0, s1) is
+  begin
+    r <= "000000";
+    if s0 = '1' then
+      r (1) <= '1';
+      r (3) <= '1';
+      r (4 downto 2) <= "101";
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/asgn01/tb_asgn03.vhdl b/testsuite/synth/asgn01/tb_asgn03.vhdl
new file mode 100644
index 000000000..f4f474c41
--- /dev/null
+++ b/testsuite/synth/asgn01/tb_asgn03.vhdl
@@ -0,0 +1,39 @@
+entity tb_asgn03 is
+end tb_asgn03;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_asgn03 is
+  signal s0 : std_logic;
+  signal s1 : std_logic;
+  signal r  : std_logic_vector (2 downto 0);
+begin
+  dut: entity work.asgn03
+    port map (s0 => s0, s1 => s1, r => r);
+
+  process
+  begin
+    s0 <= '0';
+    s1 <= '0';
+    wait for 1 ns;
+    assert r = "000" severity failure;
+
+    s0 <= '0';
+    s1 <= '1';
+    wait for 1 ns;
+    assert r = "000" severity failure;
+
+    s0 <= '1';
+    s1 <= '0';
+    wait for 1 ns;
+    assert r = "010" severity failure;
+
+    s0 <= '1';
+    s1 <= '1';
+    wait for 1 ns;
+    assert r = "011" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/asgn01/tb_asgn04.vhdl b/testsuite/synth/asgn01/tb_asgn04.vhdl
new file mode 100644
index 000000000..a51309375
--- /dev/null
+++ b/testsuite/synth/asgn01/tb_asgn04.vhdl
@@ -0,0 +1,39 @@
+entity tb_asgn04 is
+end tb_asgn04;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_asgn04 is
+  signal s0 : std_logic;
+  signal s1 : std_logic;
+  signal r  : std_logic_vector (2 downto 0);
+begin
+  dut: entity work.asgn04
+    port map (s0 => s0, s1 => s1, r => r);
+
+  process
+  begin
+    s0 <= '0';
+    s1 <= '0';
+    wait for 1 ns;
+    assert r = "000" severity failure;
+
+    s0 <= '0';
+    s1 <= '1';
+    wait for 1 ns;
+    assert r = "000" severity failure;
+
+    s0 <= '1';
+    s1 <= '0';
+    wait for 1 ns;
+    assert r = "010" severity failure;
+
+    s0 <= '1';
+    s1 <= '1';
+    wait for 1 ns;
+    assert r = "001" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/asgn01/tb_asgn05.vhdl b/testsuite/synth/asgn01/tb_asgn05.vhdl
new file mode 100644
index 000000000..09818feb9
--- /dev/null
+++ b/testsuite/synth/asgn01/tb_asgn05.vhdl
@@ -0,0 +1,29 @@
+entity tb_asgn05 is
+end tb_asgn05;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_asgn05 is
+  signal s0 : std_logic;
+  signal s1 : std_logic;
+  signal r  : std_logic_vector (5 downto 0);
+begin
+  dut: entity work.asgn05
+    port map (s0 => s0, s1 => s1, r => r);
+
+  process
+  begin
+    s0 <= '0';
+    s1 <= '0';
+    wait for 1 ns;
+    assert r = "000000" severity failure;
+
+    s0 <= '1';
+    s1 <= '0';
+    wait for 1 ns;
+    assert r = "010110" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/asgn01/testsuite.sh b/testsuite/synth/asgn01/testsuite.sh
index cb5ed0fb6..c42e9c0f1 100755
--- a/testsuite/synth/asgn01/testsuite.sh
+++ b/testsuite/synth/asgn01/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in asgn01 asgn02 arr04; do
+for t in asgn01 asgn02 asgn03 asgn04 asgn05 arr04; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean