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author | Tristan Gingold <tgingold@free.fr> | 2020-03-09 20:34:05 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-03-09 20:34:05 +0100 |
commit | 298aa852d3a080f4d26d814faf5bdaa65228949b (patch) | |
tree | bd7c88599b46a9a84481fc782d5f9526115866f0 /testsuite/synth/arr02/tb_arr01.vhdl | |
parent | 90fb8d3ae8ba631fd9eea7f7f71a0a8a65e76cfd (diff) | |
download | ghdl-298aa852d3a080f4d26d814faf5bdaa65228949b.tar.gz ghdl-298aa852d3a080f4d26d814faf5bdaa65228949b.tar.bz2 ghdl-298aa852d3a080f4d26d814faf5bdaa65228949b.zip |
testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite/synth/arr02/tb_arr01.vhdl')
-rw-r--r-- | testsuite/synth/arr02/tb_arr01.vhdl | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/testsuite/synth/arr02/tb_arr01.vhdl b/testsuite/synth/arr02/tb_arr01.vhdl new file mode 100644 index 000000000..3e5247bd9 --- /dev/null +++ b/testsuite/synth/arr02/tb_arr01.vhdl @@ -0,0 +1,49 @@ +entity tb_arr01 is +end tb_arr01; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_arr01 is + signal a : std_logic_vector (31 downto 0); + signal sel : natural range 0 to 3; + signal clk : std_logic; + signal res : std_logic_vector (7 downto 0); +begin + dut: entity work.arr01 + port map (a, sel, clk, res); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + a <= x"a1b2c3d4"; + sel <= 0; + pulse; + pulse; + assert res = x"a1" severity failure; + + sel <= 1; + pulse; + assert res = x"a1" severity failure; + + sel <= 2; + pulse; + assert res = x"b2" severity failure; + + sel <= 3; + pulse; + assert res = x"c3" severity failure; + + sel <= 0; + pulse; + assert res = x"d4" severity failure; + + wait; + end process; +end behav; |