testsuite/synth: add a test for previous commit.

4 files changed, 97 insertions, 8 deletions

diff --git a/testsuite/synth/arr01/testsuite.sh b/testsuite/synth/arr01/testsuite.sh
index f6fd4ba56..9e8ea74c5 100755
--- a/testsuite/synth/arr01/testsuite.sh
+++ b/testsuite/synth/arr01/testsuite.sh
@@ -3,14 +3,7 @@
 . ../../testenv.sh
 
 for t in arr01 arr02 arr04 arr05 arr06 arr07 arr09; do
-    analyze $t.vhdl tb_$t.vhdl
-    elab_simulate tb_$t
-    clean
-
-    synth $t.vhdl -e $t > syn_$t.vhdl
-    analyze syn_$t.vhdl tb_$t.vhdl
-    elab_simulate tb_$t
-    clean
+    synth_tb $t
 done
 
 echo "Test successful"
diff --git a/testsuite/synth/arr02/arr01.vhdl b/testsuite/synth/arr02/arr01.vhdl
new file mode 100644
index 000000000..09fc804b9
--- /dev/null
+++ b/testsuite/synth/arr02/arr01.vhdl
@@ -0,0 +1,38 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity arr01 is
+  port (
+    a : std_logic_vector (31 downto 0);
+    sel : natural range 0 to 3;
+    clk : std_logic;
+    res : out std_logic_vector (7 downto 0));
+end arr01;
+
+architecture behav of arr01 is
+  type t_mem is array (0 to 3) of std_logic_vector (7 downto 0);
+  type t_stage is record
+    sel : natural range 0 to 3;
+    val : t_mem;
+  end record;
+
+  signal s : t_stage;
+begin
+  process (clk) is
+  begin
+    if rising_edge (clk) then
+      s.sel <= sel;
+      s.val <= (a (31 downto 24),
+                a (23 downto 16),
+                a (15 downto 8),
+                a (7 downto 0));
+    end if;
+  end process;
+
+  process (clk) is
+  begin
+    if rising_edge (clk) then
+      res <= s.val (s.sel);
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/arr02/tb_arr01.vhdl b/testsuite/synth/arr02/tb_arr01.vhdl
new file mode 100644
index 000000000..3e5247bd9
--- /dev/null
+++ b/testsuite/synth/arr02/tb_arr01.vhdl
@@ -0,0 +1,49 @@
+entity tb_arr01 is
+end tb_arr01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_arr01 is
+  signal a : std_logic_vector (31 downto 0);
+  signal sel : natural range 0 to 3;
+  signal clk : std_logic;
+  signal res : std_logic_vector (7 downto 0);
+begin
+  dut: entity work.arr01
+    port map (a, sel, clk, res);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    a <= x"a1b2c3d4";
+    sel <= 0;
+    pulse;
+    pulse;
+    assert res = x"a1" severity failure;
+
+    sel <= 1;
+    pulse;
+    assert res = x"a1" severity failure;
+
+    sel <= 2;
+    pulse;
+    assert res = x"b2" severity failure;
+
+    sel <= 3;
+    pulse;
+    assert res = x"c3" severity failure;
+
+    sel <= 0;
+    pulse;
+    assert res = x"d4" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/arr02/testsuite.sh b/testsuite/synth/arr02/testsuite.sh
new file mode 100755
index 000000000..c3a077cf9
--- /dev/null
+++ b/testsuite/synth/arr02/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in arr01; do
+    synth_tb $t
+done
+
+echo "Test successful"