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author | Tristan Gingold <tgingold@free.fr> | 2019-07-30 20:57:32 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-07-30 20:57:32 +0200 |
commit | 5a846b7a38cf74f2969706dfeadad61f6bebf9e1 (patch) | |
tree | b91e14fc17d86b2b54be5166c9dd31157af4e51e /testsuite/synth/arr02/dpram3.vhdl | |
parent | ca8803efc8b2c52b813bf22df814c26e139889e2 (diff) | |
download | ghdl-5a846b7a38cf74f2969706dfeadad61f6bebf9e1.tar.gz ghdl-5a846b7a38cf74f2969706dfeadad61f6bebf9e1.tar.bz2 ghdl-5a846b7a38cf74f2969706dfeadad61f6bebf9e1.zip |
synth: add dpram3 test.
Diffstat (limited to 'testsuite/synth/arr02/dpram3.vhdl')
-rw-r--r-- | testsuite/synth/arr02/dpram3.vhdl | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/testsuite/synth/arr02/dpram3.vhdl b/testsuite/synth/arr02/dpram3.vhdl new file mode 100644 index 000000000..a04478809 --- /dev/null +++ b/testsuite/synth/arr02/dpram3.vhdl @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity dpram3 is + port (raddr : std_logic_vector (3 downto 0); + rdat : out std_logic_vector (7 downto 0); + waddr : std_logic_vector (3 downto 0); + wdat : std_logic_vector (7 downto 0); + clk : std_logic); +end dpram3; + +architecture behav of dpram3 is +begin + process (clk) + type memtype is array (0 to 15) of std_logic_vector (7 downto 0); + variable mem : memtype; + begin + if rising_edge (clk) then + rdat <= mem (to_integer(unsigned (raddr))); + mem (to_integer(unsigned (waddr))) := wdat; + end if; + end process; +end behav; |