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author | Tristan Gingold <tgingold@free.fr> | 2020-03-09 20:34:05 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-03-09 20:34:05 +0100 |
commit | 298aa852d3a080f4d26d814faf5bdaa65228949b (patch) | |
tree | bd7c88599b46a9a84481fc782d5f9526115866f0 /testsuite/synth/arr02/arr01.vhdl | |
parent | 90fb8d3ae8ba631fd9eea7f7f71a0a8a65e76cfd (diff) | |
download | ghdl-298aa852d3a080f4d26d814faf5bdaa65228949b.tar.gz ghdl-298aa852d3a080f4d26d814faf5bdaa65228949b.tar.bz2 ghdl-298aa852d3a080f4d26d814faf5bdaa65228949b.zip |
testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite/synth/arr02/arr01.vhdl')
-rw-r--r-- | testsuite/synth/arr02/arr01.vhdl | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/testsuite/synth/arr02/arr01.vhdl b/testsuite/synth/arr02/arr01.vhdl new file mode 100644 index 000000000..09fc804b9 --- /dev/null +++ b/testsuite/synth/arr02/arr01.vhdl @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity arr01 is + port ( + a : std_logic_vector (31 downto 0); + sel : natural range 0 to 3; + clk : std_logic; + res : out std_logic_vector (7 downto 0)); +end arr01; + +architecture behav of arr01 is + type t_mem is array (0 to 3) of std_logic_vector (7 downto 0); + type t_stage is record + sel : natural range 0 to 3; + val : t_mem; + end record; + + signal s : t_stage; +begin + process (clk) is + begin + if rising_edge (clk) then + s.sel <= sel; + s.val <= (a (31 downto 24), + a (23 downto 16), + a (15 downto 8), + a (7 downto 0)); + end if; + end process; + + process (clk) is + begin + if rising_edge (clk) then + res <= s.val (s.sel); + end if; + end process; +end behav; |