Dependency Graphs (#2308)

* Further fixes to the example code.

* Bumped dependencies.

* Fixed Debouncer example code.

* Some more cleanup.

* Black's opinion.

* Run with pyVHDLModel dev-branch.

* Fixed imports for Name.

* Fixed test case.

* Added a formatter to write dependency graphs and hierarchy as graphml.

* Improved GraphML formatting.

* Write compile order graph.

* Computing compile order.

* Bumped dependencies.

* Black's opinion.

* Fixed incorrect dependency.

1 files changed, 17 insertions, 0 deletions

diff --git a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl
index f67f99c72..3755e4575 100644
--- a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl
+++ b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl
@@ -30,4 +30,21 @@ package StopWatch_pkg is
 			Seg7Code  : out std_logic_vector(7 downto 0)
 		);
 	end component;
+
+	component seg7_Display is
+		generic (
+			CLOCK_PERIOD  : time := 10 ns;
+			REFRESH_RATE  : time := 200 us;
+			DIGITS        : positive
+		);
+		port (
+			Clock         : in  std_logic;
+
+			DigitValues   : in  T_BCD_Vector(DIGITS - 1 downto 0);
+			DotValues     : in  std_logic_vector(DIGITS - 1 downto 0) := (others => '0');
+
+			Seg7_Segments : out std_logic_vector(7 downto 0);
+			Seg7_Selects  : out std_logic_vector(DIGITS - 1 downto 0)
+		);
+	end component;
 end package;