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| author | Tristan Gingold <tgingold@free.fr> | 2018-12-04 04:48:50 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2018-12-04 04:48:50 +0100 |
| commit | 4ee9742dfe7e97ecd1bc4dd8fb323591ae57b118 (patch) | |
| tree | 927e190c938dce79955e4458ce6d5d8ddc0644d1 /testsuite/gna/issue715 | |
| parent | 8fb41b61659c2ee3d86dc9aebb0b60e5582a5ac1 (diff) | |
| download | ghdl-4ee9742dfe7e97ecd1bc4dd8fb323591ae57b118.tar.gz ghdl-4ee9742dfe7e97ecd1bc4dd8fb323591ae57b118.tar.bz2 ghdl-4ee9742dfe7e97ecd1bc4dd8fb323591ae57b118.zip | |
Add reproducer for #715
Diffstat (limited to 'testsuite/gna/issue715')
| -rw-r--r-- | testsuite/gna/issue715/IntDemo.mem | 144 | ||||
| -rw-r--r-- | testsuite/gna/issue715/LRAM.vhdl | 78 | ||||
| -rwxr-xr-x | testsuite/gna/issue715/testsuite.sh | 11 |
3 files changed, 233 insertions, 0 deletions
diff --git a/testsuite/gna/issue715/IntDemo.mem b/testsuite/gna/issue715/IntDemo.mem new file mode 100644 index 000000000..6b19c3c30 --- /dev/null +++ b/testsuite/gna/issue715/IntDemo.mem @@ -0,0 +1,144 @@ +E7000053
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diff --git a/testsuite/gna/issue715/LRAM.vhdl b/testsuite/gna/issue715/LRAM.vhdl new file mode 100644 index 000000000..e6ec79bb6 --- /dev/null +++ b/testsuite/gna/issue715/LRAM.vhdl @@ -0,0 +1,78 @@ +------------------------------------------------------------------------------- +-- +-- walter d. gallegos +-- www.waltergallegos.com +-- Programmable Logic Consulting +-- +-- Este archivo y documentacion son propiedad intelectual de Walter D. Gallegos +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL, IEEE.NUMERIC_STD.ALL; +USE STD.TextIO.ALL; + +ENTITY LRAM IS +GENERIC ( size : INTEGER := 14; fName : STRING := "IntDemo.mem"; startAdr : INTEGER := 0); + PORT ( + CLOCK : IN STD_LOGIC; + WR : IN STD_LOGIC; + BEA : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + DIA : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + DOA : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + ADRA : IN STD_LOGIC_VECTOR (size-1 DOWNTO 0); + DOB : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + ADRB : IN STD_LOGIC_VECTOR (size-1 DOWNTO 0) + ); +END LRAM; + +ARCHITECTURE WDG0 OF LRAM IS + + CONSTANT depth : INTEGER := (2**size)-1; + TYPE LocalRAMDesc IS ARRAY (0 TO depth) OF STD_LOGIC_VECTOR(31 DOWNTO 0); + + IMPURE FUNCTION Init (fName : STRING) RETURN LocalRAMDesc IS + FILE f : TEXT OPEN READ_MODE IS fName; + VARIABLE l : LINE; + VARIABLE b : STD_LOGIC_VECTOR(31 DOWNTO 0); + VARIABLE m : LocalRAMDesc := (OTHERS => (OTHERS => '0')); + BEGIN + FOR i IN startAdr TO depth LOOP + EXIT WHEN endfile(f); + IF (i = depth) THEN + REPORT "LRAM : Error memory full " SEVERITY FAILURE; + END IF; + readline(f, l); hread(l, b); + m(i) := STD_LOGIC_VECTOR(RESIZE(UNSIGNED(b), 32)); + END LOOP; + REPORT ("LRAM : loaded from " & fName & LF) SEVERITY NOTE; + RETURN m; + END FUNCTION; + + SIGNAL LocalRAM : LocalRAMDesc := Init(fName); + SIGNAL data, code : STD_LOGIC_VECTOR(31 DOWNTO 0); + + -- XILINX ATTRIBUTE + ATTRIBUTE ram_style : STRING; + ATTRIBUTE ram_style OF LocalRAM : SIGNAL IS "block"; + -- XILINX END ATTRIBUTE + +BEGIN + + CodeDataMemory : PROCESS(CLOCK) + BEGIN + IF rising_edge(CLOCK) THEN + FOR i IN DIA'RANGE LOOP + IF (BEA(i/8) AND WR)= '1' THEN + LocalRAM(TO_INTEGER(UNSIGNED(ADRA)))(i) <= DIA(i); + END IF; + END LOOP; + data <= LocalRAM(TO_INTEGER(UNSIGNED(ADRA))); + code <= LocalRAM(TO_INTEGER(UNSIGNED(ADRB))); + END IF; + END PROCESS CodeDataMemory; + + DOA <= data; + DOB <= code; + +END WDG0; diff --git a/testsuite/gna/issue715/testsuite.sh b/testsuite/gna/issue715/testsuite.sh new file mode 100755 index 000000000..36521da80 --- /dev/null +++ b/testsuite/gna/issue715/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze LRAM.vhdl +elab_simulate LRAM --max-stack-alloc=0 + +clean + +echo "Test successful" |