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author | Tristan Gingold <tgingold@free.fr> | 2017-01-24 08:51:38 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2017-01-24 08:51:38 +0100 |
commit | bf028b7f7406f538d6acf6edab8e8b2d367aa6c0 (patch) | |
tree | 997f5d37238d4a850452278cca6deee22917386a /testsuite/gna/issue262/repro.vhdl | |
parent | a076edcd1f817f82b2a5dca031668ebb99f308d6 (diff) | |
download | ghdl-bf028b7f7406f538d6acf6edab8e8b2d367aa6c0.tar.gz ghdl-bf028b7f7406f538d6acf6edab8e8b2d367aa6c0.tar.bz2 ghdl-bf028b7f7406f538d6acf6edab8e8b2d367aa6c0.zip |
Add testcase for #262
Diffstat (limited to 'testsuite/gna/issue262/repro.vhdl')
-rw-r--r-- | testsuite/gna/issue262/repro.vhdl | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/testsuite/gna/issue262/repro.vhdl b/testsuite/gna/issue262/repro.vhdl new file mode 100644 index 000000000..bb4dd2965 --- /dev/null +++ b/testsuite/gna/issue262/repro.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity repro is +end; + +architecture behav of repro is +begin + process + variable result : std_ulogic; + begin + result := std_ulogic_vector'("-000") ?/= std_ulogic_vector'("0000"); + result := std_ulogic_vector'("-000") ?= std_ulogic_vector'("0000"); + wait; + end process; +end behav; |