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| author | Tristan Gingold <tgingold@free.fr> | 2021-07-28 22:09:54 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-07-28 22:09:54 +0200 |
| commit | f9036aba4d5d18cf2cf4893589e8a41ea9b064b7 (patch) | |
| tree | bf89fbbf05bb7ecc3171e3fd8fc4eb7db5599240 /testsuite/gna/issue1823/entity3.vhdl | |
| parent | 5d6232f08fb5597aa3833f69e52ecbb4be250071 (diff) | |
| download | ghdl-f9036aba4d5d18cf2cf4893589e8a41ea9b064b7.tar.gz ghdl-f9036aba4d5d18cf2cf4893589e8a41ea9b064b7.tar.bz2 ghdl-f9036aba4d5d18cf2cf4893589e8a41ea9b064b7.zip | |
testsuite/gna: add a test for #1823
Diffstat (limited to 'testsuite/gna/issue1823/entity3.vhdl')
| -rw-r--r-- | testsuite/gna/issue1823/entity3.vhdl | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/testsuite/gna/issue1823/entity3.vhdl b/testsuite/gna/issue1823/entity3.vhdl new file mode 100644 index 000000000..0e502cb96 --- /dev/null +++ b/testsuite/gna/issue1823/entity3.vhdl @@ -0,0 +1,11 @@ +entity entity3 is +end; + +architecture behav of entity3 is + signal Clock : bit; +begin + inst2: counter2.all + port map ( + clk => Clock + ); +end architecture behav; |