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| author | Tristan Gingold <tgingold@free.fr> | 2021-04-07 21:37:10 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-04-07 21:37:37 +0200 |
| commit | 2d3991ff1b325d556ac922c679ffaf39bcdb6815 (patch) | |
| tree | e348cfbb23d960d47510bf4536d14bdfd3b05784 /testsuite/gna/issue1715/mwe-repro.vhdl | |
| parent | 927454548c6044c6a7383d8cc447bdfb39141ced (diff) | |
| download | ghdl-2d3991ff1b325d556ac922c679ffaf39bcdb6815.tar.gz ghdl-2d3991ff1b325d556ac922c679ffaf39bcdb6815.tar.bz2 ghdl-2d3991ff1b325d556ac922c679ffaf39bcdb6815.zip | |
testsuite/gna: add a test for #1715
Diffstat (limited to 'testsuite/gna/issue1715/mwe-repro.vhdl')
| -rw-r--r-- | testsuite/gna/issue1715/mwe-repro.vhdl | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/testsuite/gna/issue1715/mwe-repro.vhdl b/testsuite/gna/issue1715/mwe-repro.vhdl new file mode 100644 index 000000000..5845538c4 --- /dev/null +++ b/testsuite/gna/issue1715/mwe-repro.vhdl @@ -0,0 +1,25 @@ +entity comp1 is + port ( + a_i : in bit_vector(3 downto 0) + ); +end entity; + +architecture arch of comp1 is +begin +end arch; + +entity mwe is +end entity; + +architecture arch of mwe is + signal clk : bit := '0'; + signal a : bit_vector(3 downto 0); +begin + process + begin + wait until clk'stable; + end process; + + x_comp1 : entity work.comp1 + port map (a_i => a or a); +end arch; |